Neil H. E. Weste, David Money Harris  | 경문사

37,050원  | 20220820  | 9789813350519

이 책은 CMOS VLSI의 기초에서부터 최근의 첨단 기술 이론 및 동향까지 전반적인 기술을 깊이 있게 다루었으며, 저자들의 풍부한 경험에 따른 많은 예제를 통하여 이해하기 쉽도록 설명되어 있다. 특히 2005년에 번역되었던 3판과 비교할 때, 트랜지스터 이론, 공정 기술, 회로 특성, CMOS 논리 회로, 순차 회로 설계, 데이터 경로, 메모리, I/O, 설계 방법 및 테스트 방법 등 전반적인 내용이 발전되고 변화한 기술들로 대체되어 있다. 또한 위에 열거한 기존의 주제들 이외에도 PLL과 DLL 등 최근의 기술적인 추세에 필요한 기술들이 추가되어서 구체적이면서도 널리 활용되는 회로 집단 및 서브시스템들을 다양하게 섭렵할 수 있도록 배려하였다. 이 책이 CMOS VLSI를 이해하고 활용하기 위한 완벽에 가까운 지침서 역할을 하는 데 의심의 여지가 없다. 집적회로 설계의 빠른 변화를 반영하여 많은 부분을 새롭게 개정한 이 책은 시스템 수준부터 회로 수준까지 기본적인 원칙의 예와 좋은 설계 예시를 소개했다. 저자들은 칩 설계의 최신 예시를 설명하기 위해 많은 강의 경험을 활용했으며, 인텔, 시스코, 벨연구소에서의 전문적인 경험을 공유함으로써 현실적인 관점을 주제에 포함했다. 제4판의 새로운 특징 ㆍ 저전력 설계에 관한 깊이 있는 내용 ㆍ 변이의 원인과 영향에 대한 자세한 설명 ㆍ 65nm 예제의 나노미터 기술 설계 ㆍ PLL, DLL, 고속 I/O ㆍ 최신 메모리 설계의 예시 ㆍ 데이터 경로 서브시스템의 최신 내용

Neil H. E. Weste, David Money Harris  | 한티에듀

0원  | 20210205  | 9788945006455

이 책은 CMOS VLSI의 기초에서부터 최근의 첨단 기술 이론 및 동향까지 전반적인 기술을 깊이 있게 다루었으며, 저자들의 풍부한 경험에 따른 많은 예제를 통하여 이해하기 쉽도록 설명되어 있다. 특히 2005년에 번역되었던 3판과 비교할 때, 트랜지스터 이론, 공정 기술, 회로 특성, CMOS 논리 회로, 순차 회로 설계, 데이터 경로, 메모리, I/O, 설계 방법 및 테스트 방법 등 전반적인 내용이 발전되고 변화한 기술들로 대체되어 있다. 또한 위에 열거한 기존의 주제들 이외에도 PLL과 DLL 등 최근의 기술적인 추세에 필요한 기술들이 추가되어서 구체적이면서도 널리 활용되는 회로 집단 및 서브시스템들을 다양하게 섭렵할 수 있도록 배려하였다. 이 책이 CMOS VLSI를 이해하고 활용하기 위한 완벽에 가까운 지침서 역할을 하는 데 의심의 여지가 없다. 집적회로 설계의 빠른 변화를 반영하여 많은 부분을 새롭게 개정한 이 책은 시스템 수준부터 회로 수준까지 기본적인 원칙의 예와 좋은 설계 예시를 소개했다. 저자들은 칩 설계의 최신 예시를 설명하기 위해 많은 강의 경험을 활용했으며, 인텔, 시스코, 벨연구소에서의 전문적인 경험을 공유함으로써 현실적인 관점을 주제에 포함했다. 제4판의 새로운 특징 ㆍ 저전력 설계에 관한 깊이 있는 내용 ㆍ 변이의 원인과 영향에 대한 자세한 설명 ㆍ 65nm 예제의 나노미터 기술 설계 ㆍ PLL, DLL, 고속 I/O ㆍ 최신 메모리 설계의 예시 ㆍ 데이터 경로 서브시스템의 최신 내용

 | Springer Nature B.V.

71,480원  | 20130317  | 9781475728248

Silicon-On-Insulator (SOI) CMOS technology has been regarded as another major technology for VLSI in addition to bulk CMOS technology. Owing to the buried oxide structure, SOI technology offers superior CMOS devices with higher speed, high density, and reduced second order effects for deep-submicron low-voltage, low-power VLSI circuits applications.

 | Hutson Street Press

28,510원  | 20250522  | 9781025156415

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it.

 | Hutson Street Press

53,530원  | 20250522  | 9781025152776

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it.

 | KS OmniScriptum Publishing

175,170원  | 20110823  | 9783845424163

Continuous scaling in the technology feature size and hence the supply voltage, has directed analog designers to change the signal representation from voltage domain to current domain. That is why the high performance current-mode building blocks have received a great deal of interest. The current-mode is better than the voltage-mode in such aspects like: lower voltage supplies, lower power consumption, wider dynamic range and higher bandwidth.

 | KS OmniScriptum Publishing

107,250원  | 20100603  | 9783838301280

Power dissipation is a critical parameter in digital design for the implementation of high performance portable, battery operated systems, such as wireless communications systems. Clocked or synchronous digital designs consume a significant amount of power associated with coordinating the operation of millions of transistors at GHz clock rates. Besides, the operating speed of such systems is limited by the slowest functional logic unit.

 | KS OmniScriptum Publishing

144,780원  | 20250825  | 9786208480622

The semiconductor industry has been following Moore's law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size.

Kundu, Sandip  | McGraw-Hill Companies

139,000원  | 20100401  | 9780071635196

Cutting-edge Design for Manufacturability Techniques for Nanoscale CMOS VLSI Circuits

Weste, Neil H. E./ Harris, David  | Addison-Wesley

0원  | 20040511  | 9780321149015

The extensively revised 3rd edition of CMOS VLSI Design details modern techniques for the design of complex and high performance CMOS Systems-on-Chip. The authors draw upon extensive industry and classroom experience to explain modern practices of chip design. The introductory chapter covers transistor operation, CMOS gate design, fabrication, and layout at a level accessible to anyone with an elementary knowledge of digital electornics. Later chapters beuild up an in-depth discussion of the design of complex, high performance, low power CMOS Systems-on-Chip.

Kuo, James B./ Lou, Jea-Hong  | Wiley

0원  | 19990113  | 9780471321057

Low-voltage very large scale integration (VLSI) circuits represent the electronics of the future. All electronic products are striving to reduce power consumption to create more economical, efficient, and compact devices. Despite the inevitable trend towards low-voltage, few books address the technology needed. Geared to the needs of engineers and designers in the field, this comprehensive volume presents a remarkably detailed analysis of one of today's hottest and most compelling research techniques for VLSI systems.An Instructor's Manual presenting detailed solutions to all the problems in the book is available from the Wiley editorial department.

Kuo, James B./ Su, Ker-Wei  | Kluwer

303,850원  | 19981101  | 9780792382720

Silicon-On-Insulator (SOI) CMOS technology has been regarded as another major technology for VLSI in addition to bulk CMOS technology. Owing to the buried oxide structure, SOI technology offers superior CMOS devices with higher speed, high density, and reduced second order effects for deep-submicron low-voltage, low-power VLSI circuits applications. In addition to VLSI applications, and because of its outstanding properties, SOI technology has been used to realize communication circuits, microwave devices, BICMOS devices, and even fiber optics applications. CMOS VLSI Engineering: Silicon-On-Insulator addresses three key factors in engineering SOI CMOS VLSI - processing technology, device modelling, and circuit designs are all covered with their mutual interactions. Starting from the SOI CMOS processing technology and the SOI CMOS digital and analog circuits, behaviors of the SOI CMOS devices are presented, followed by a CAD program, ST-SPICE, which incorporates models for deep-submicron fully-depleted mesa-isolated SOI CMOS devices and special purpose SOI devices including polysilicon TFTs. CMOS VLSI Engineering: Silicon-On-Insulator is written for undergraduate senior students and first-year graduate students interested in CMOS VLSI. It will also be suitable for electrical engineering professionals interested in microelectronics.

Weste, Neil, H. E./ Harris, David Money  | Pearson

244,870원  | 20100301  | 9780321547743

This butler is just too good to be true ...

Sachdev, Manoj  | Springer

0원  | 20210101  | 9780387465463

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Iniewski, Krzysztof  | McGraw-Hill

260,610원  | 20130104  | 9780071755658

A pioneering guide to the design of integrated circuits on the nanoscale level, with a focus on emerging and future technologies