| KS OmniScriptum Publishing

111,750원  | 20120716  | 9783659168451

CMOS digital ICs are enabling the technology for the modern information age. Digital systems handle large amounts of information at high speeds. Such products demand low-priced memories with low-power consumption, high-speed operation, high density, and small package size. The architecture of the memory structure has a considerable impact on the performance of the system. Over the years, technology advances have been driven by memory designs of higher and higher density.

 | KS OmniScriptum Publishing

145,270원  | 20130109  | 9783659320378

Static random-access memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-end workstation and microprocessor applications. For almost all fields of applications, semiconductor memory has been a key enabling technology. It is forecasted that embedded memory in SOC designs will cover up to 90% of the total chip area. A representative example is the use of cache memory in microprocessors.

 | CRC Press

118,620원  | 20250526  | 9781032100593

This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate, graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering.

 | Springer

316,600원  | 20080601  | 9781402083624

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells.

 | KS OmniScriptum Publishing

130,370원  | 20120529  | 9783659124976

This book considers the following problems in the domain of test and reliability of SRAM memories: optimizing test flow using stress conditions; statistical simulation for very low probabilities; variability analysis of an SRAM test-chip; fault tolerance in random addressed memories. Although the problems considered are all related to SRAM, some solutions found may also be applied in other domains. The Monte-carlo based simulation method described here is a general purpose method.

 | Verlag Unser Wissen

74,500원  | 20240821  | 9786207969302

Dieses Buch beschreibt das SRAM-Entwurfskonzept in FinFET-Technologien unter Verwendung der einzigartigen Merkmale nicht-planarer Bauelemente mit doppeltem Gate. Der fur das Design von FinFETs erforderliche Parameterraum wird erforscht. Es wird eine Vielzahl von SRAM-Entwurfstechniken vorgestellt, die die Vorteile von Konfigurationen mit gebundenen und unabhangigen Gates nutzen.

 | Edicoes Nosso Conhecimento

108,020원  | 20241129  | 9786208332068

Neste trabalho, e apresentada a nova celula SRAM de extremidade unica 5T e 6T. Este transistor e uma celula de alta densidade ou ocupa menos area do que a celula SRAM 6T convencional. A corrente de fuga desta celula e muito baixa em comparacao com outras celulas 5T ou 6T convencionais. E necessario um circuito de pre-carga para esta celula, tal como na celula SRAM 6T convencional. Esta celula e igualmente eficiente em termos de consumo de energia.

 | KS OmniScriptum Publishing

113,610원  | 20120530  | 9783659114168

Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed.

 | Edicoes Nosso Conhecimento

74,500원  | 20240821  | 9786207969340

Este livro descreve o conceito de concecao de SRAM em tecnologias FinFET utilizando carateristicas unicas de dispositivos nao planares de dupla porta. Sera explorado o espaco de parametros necessario para a concecao de FinFETs. Serao apresentadas varias tecnicas de concecao de SRAM que exploram as vantagens das configuracoes controladas por porta ligada e porta independente.

 | Editions Notre Savoir

108,020원  | 20241129  | 9786208332006

Ce travail presente une nouvelle cellule SRAM 5T et 6T a extremite unique. Ce transistor est une cellule a haute densite ou prend moins de place qu'une cellule SRAM 6T conventionnelle. Le courant de fuite de cette cellule est tres faible par rapport aux autres cellules 5T ou 6T conventionnelles. Un circuit de precharge est necessaire pour cette cellule, comme c'est le cas pour la cellule SRAM 6T conventionnelle. Cette cellule est egalement econome en energie.

 | Edizioni Sapienza

108,020원  | 20241129  | 9786208332020

In questo lavoro viene presentata una nuova cella SRAM single ended a 5T e 6T. Questo transistor e una cella ad alta densita o occupa un'area inferiore rispetto alle celle SRAM convenzionali a 6T. La corrente di dispersione di questa cella e molto bassa rispetto alle altre celle 5T o 6T convenzionali. Per questa cella e necessario un circuito di precarica come per le celle SRAM convenzionali a 6T. Questa cella e anche efficiente dal punto di vista energetico.

Kastensmidt, Fernanda Lima  | Springer Verlag Gmbh

0원  | 20210101  | 9780387310688

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.

 | KS OmniScriptum Publishing

115,470원  | 20120620  | 9783848435845

As the operating voltage scales down with the technology, SRAM cells have focus at the stability. The 9T SRAM with inherent data stability and capability of reducing the leakage power is adopted to meet the stringent requirements of the low power designs. The circuit techniques used to reduce the power dissipation and delay of these components has been explored optimum power consumption is obtained.

 | Editions Notre Savoir

74,500원  | 20240821  | 9786207969319

Ce livre decrit le concept de conception des SRAM dans les technologies FinFET en utilisant les caracteristiques uniques des dispositifs non planaires a double grille. L'espace des parametres necessaires a la conception des FinFET sera explore. Diverses techniques de conception de SRAM seront presentees en exploitant les avantages des configurations controlees par des portes liees et des portes independantes.

 | Edizioni Sapienza

74,500원  | 20240821  | 9786207969333

Questo libro descrive il concetto di progettazione di SRAM nelle tecnologie FinFET utilizzando le caratteristiche uniche dei dispositivi a doppia griglia non planari. Viene esplorato lo spazio dei parametri richiesto per la progettazione dei FinFET. Verranno presentate diverse tecniche di progettazione di SRAM che sfruttano i vantaggi delle configurazioni a gate vincolato e a gate indipendente.