스튜어트 서덜랜드  | 홍릉과학출판사

30,000원  | 20090925  | 9788972837718

『디자인을 위한 System verilog』는 Verilog를 잘 아는 사람이 System Verilog에 대해 공부하가조 할 때 유용한 책이다.Verilog를 잘모르면 이 책을 이해할 수가 없고 특히System Verilog은 C++에서 많은 개념을 가지고 왔기 때문에 C++을 좀 알고 잇으면 System Verilog를 보다 더 쉽게 이해 할 수 있을 것이다.

Mano  | Pearson

44,550원  | 20180910  | 9781292231167

For introductory courses on digital design in an Electrical Engineering, Computer Engineering, or Computer Science department. A clear and accessible approach to the basic tools, concepts, and applications of digital design A modern update to a classic, authoritative text, Digital Design, 6th Edition teaches the fundamental concepts of digital design in a clear, accessible manner.

Vijayaraghavan, Srikanth/ Ramanathan, Meyyappan  | Springer

297,480원  | 20050801  | 9780387260495

SystemVerilog language consists of three very specific areas of constructs -- design, assertions and testbench. Assertions add a whole new dimension to the ASIC verification process. Assertions provide a better way to do verification proactively. Traditionally, engineers are used to writing verilog test benches that help simulate their design. Verilog is a procedural language and is very limited in capabilities to handle the complex Asic's built today. SystemVerilog assertions (SVA) are a declarative and temporal language that provides excellent control over time and parallelism. This provides the designers a very strong tool to solve their verification problems. While the language is built solid, the thinking is very different from the user's perspective when compared to standard verilog language. The concept is still very new and there is not enough expertise in the field to adopt this methodology and be successful. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book will be the practical guide that will help people to understand this new methodology. "Today's SoC complexity coupled with time-to-market and first-silicon success pressures make assertion based verification a requirement and this book points the way to effective use of assertions." Satish S. Iyengar, Director, ASIC Engineering, Crimson Microsystems, Inc. "This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA). First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate. The many real life examples, provided throughout the book, are especially useful." Irwan Sie, Director, IC Design, ESS Technology, Inc. "SystemVerilog Assertions is a new language that can find and isolate bugs early in the design cycle. This book shows how to verify complex protocols and memories using SVA with seeral examples. This book is a good reference guide for both design and verification engineers." Derick Lin, Senior Director, Engineering, Airgo Networks, Inc.

Mehta, Ashok B.  | Springer

115,530원  | 20201018  | 9783030247393

Mintz, Mike/ Ekendahl, Robert  | Springer

297,480원  | 20070522  | 9780387717388

Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task. With this handbook'the first to focus on applying OOP to SystemVerilog'we'll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more "reasonable" code, and build efficient and reusable verification components. Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples. You can copy and paste from these examples, which are all based on an open-source, vendor-neutral framework (with code freely available at www.trusster.com). Learn about OOP techniques such as these: Creating classes'code interfaces, factory functions, reuse Connecting classes'pointers, inheritance, channels Using "correct by construction"'strong typing, base classes Packaging it up'singletons, static methods, packages This handbook guides the user in applying OOP techniques for verification. Mike and Robert have captured their years of experience in a clear and easy-to-read handbook. The examples are complete, and the code is available for you to get started right away. Highly recommended. Thomas D. Tessier, President, t2design, Inc. This handbook contains a lot of useful advice for any verification engineer wanting to create a class-based testbench, regardless of the framework/methodology used. I recommend Hardware Verification with SystemVerilog to anyone who wants a greater understanding of how best to use OOP with SystemVerilog. Dr. David Long, Senior Consultant, Doulos This is a fantastic book that not only shows how to use SystemVerilog and Object-Oriented Programming for verification, but also provides practical examples that are open source! Stephanie Waters, Field Applications Engineer, Cadence Design Systems I have been using SystemVerilog for two years in my research, and this is by far the best book I have found about how to achieve professional grade verification. I will apply these techniques on my future projects. Dr. Oswaldo Cadenas, Lecturer, Electronic Engineering, University of Reading, U.K.

Navabi, Zainalabedin  | McGraw-Hill

0원  | 20210101  | 9780071445641

Lin, Ming-Bo  | Wiley

40,000원  | 20090203  | 9780470823231

System-on-a-chip (SoC) has become an essential technique to lower product costs and maximize power efficiency, particularly as the mobility and size requirements of electronics continues to grow. It has therefore become increasingly important for electrical engineers to develop a strong understanding of the key stages of hardware description language (HDL) design flow based on cell-based libraries or field-programmable gate array (FPGA) devices. Honed and revised through years of classroom use, Lin focuses on developing, verifying, and synthesizing designs of practical digital systems using the most widely used hardware description Language: Verilog HDL. Explains how to perform synthesis and verification to achieve optimized synthesis results and compiler times Offers complete coverage of Verilog syntax Illustrates the entire design and verification flow using an FPGA case study Presents real-world design examples such as LED and LCD displays, GPIO, UART, timers, and CPUs Emphasizes design/implementation tradeoff options, with coverage of ASICs and FPGAs Provides an introduction to design for testability Gives readers deeper understanding by using problems and review questions in each chapter Comes with downloadable Verilog HDL source code for most examples in the text Includes presentation slides of all book figures for student reference Digital System Designs and Practices Using Verilog HDL and FPGAs is an ideal textbook for either fundamental or advanced digital design courses beyond the digital logic design level. Design engineers who want to become more proficient users of Verilog HDL as well as design FPGAs with greater speed and accuracy will find this book indispensable.

Unsalan, Cem  | McGraw-Hill

144,900원  | 20170710  | 9781259837906

Master the art of FPGA digital system design with Verilog and VHDL

Chu, Pong P.  | John Wiley & Sons Inc

223,780원  | 20140212  | 9781118011034

* Offers experiment problems with various levels of difficulties in the end of each chapter. * Provides Complete code listing. * Offers Multi-week projects in the end of each chapter. * Includes annotated bibliographic notes for further reading.