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· 제목 : Verilog Digital System Design (Hardcover, CD-ROM, 2nd) (RT Level Synthesis, Testbench and Verification)
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전기공학
· ISBN : 9780071445641
· 쪽수 : 384쪽
· 출판일 : 2005-09-30
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전기공학
· ISBN : 9780071445641
· 쪽수 : 384쪽
· 출판일 : 2005-09-30
목차
Chapter 1: Design Automation with Verilog
Chapter 2: Register Transfer Level Design with Verilog
Chapter 3: Verilog Language Concepts
Chapter 4: Combinational Circuit Description
Chapter 5: Sequential Circuit Description
Chapter 6: Component Test and Verification
Chapter 7: Detailed Modeling
Chapter 8: RT Level Design and Test
Appendix A: List of Keywords
Appendix B: Frequently Used Sysytem Tasks and Functions
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors
Chapter 3: Verilog Language Concepts
Chapter 4: Combinational Circuit Description
Chapter 5: Sequential Circuit Description
Chapter 6: Component Test and Verification
Chapter 7: Detailed Modeling
Chapter 8: RT Level Design and Test
Appendix A: List of Keywords
Appendix B: Frequently Used Sysytem Tasks and Functions
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors
Chapter 5: Sequential Circuit Description
Chapter 6: Component Test and Verification
Chapter 7: Detailed Modeling
Chapter 8: RT Level Design and Test
Appendix A: List of Keywords
Appendix B: Frequently Used Sysytem Tasks and Functions
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors
Chapter 7: Detailed Modeling
Chapter 8: RT Level Design and Test
Appendix A: List of Keywords
Appendix B: Frequently Used Sysytem Tasks and Functions
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors
Appendix A: List of Keywords
Appendix B: Frequently Used Sysytem Tasks and Functions
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors
Appendix E: Verilog Assertion Monitors
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