Stress and Strain Engineering at Nanoscale in Semiconductor Devices (Hardcover)

Chapter 1. Introduction 1.1 Beyond Silicon 1.2 Towards New Architectures 1.3 Future of nano-CMOS Technology 1.4 Technology CAD Chapter 2. Simulation Environment 2.1 Synopsys TCAD Tools 2.2 Silvaco TCAD Tools 2.3 VSP Simulation Software 2.4 MINIMOS-NT 2.5 Technology CAD Simulation 2.6 Device Simulation 2.7 Mechanical Stress Modeling Chapter 3. Stress Generation Techniques in CMOS Technology 3.1 Stress/Strain Modeling 3.2 Stress/Strain Mapping in Semiconductor Devices 3.3 Simulation of Deformation 3.4 Epitaxial Layers: Stress Simulation 3.5 Simulation Case Studies Chapter 4. Electronic Properties of Engineered Substrates 4.1 Energy Gap and Band Structure 4.2 Piezoresistivity Mobility Modeling 4.3 Mobility in a Transistor 4.4 Simulation Case Studies Chapter 5. Bulk-Si FinFETs 5.1 Operating Principle 5.2 FinFETs: Scaling and Design Issues 5.3 Virtual Fabrication of Bulk-Si TriGate FinFETs 5.4 Stress Tuning using epi-SiGe Source/Darin Stressor 5.5 Electrical Performance Chapter 6. Strain-Engineered FinFETs at NanoScale 6.1 Design and Simulation at 7N 6.2 Design Issues 6.3 Variability Due to Geometry Change 6.4 Variability Due to Metal Grain Granularity 6.5 Variability due to Random Discrete Dopants Chapter 7. Technology CAD of III-Nitride Based Devices 7.1 History of Nitride Technology 7.2 Material Properties III-N 7.3 Optical properties 7.4 Polarization in Nitride Semiconductors 7.5 HEMT Structure 7.6 Simulation Case Studies Chapter 8. Strain-Engineered SiGe Channel TFT for Flexible Electronics 8.1 Heteroepitaxy of Si-Ge Layers 8.2 Device Structure Generation 8.3 Stress Analysis 8.4 Device Simulation