Logic Synthesis Using Synopsys(r) (Hardcover, 2, 1997)

Foreword. Preface. About the Authors. 1. High-Level Design Methodology Overview. 2. VHDL/Verilog Coding for Synthesis. 3. Pre and Post-Synthesis Simulation. 4. Constraining and Optimizing Designs - I. 5. Constraining and Optimizing Designs - II. 6. Links to Layout. 7. FPGA Synthesis. 8. Design for Testability. 9. Interfacing Between CAD Tools. 10. Design Re-Use Using DesignWare. 11. Behavioral Synthesis - An Introduction. Appendix A: Sample dc_shell Scripts. Sample Synopsys Technology Library. Sample Synopsys Technology RAM Library Model. Subject Index.