Digital Integrated Circuits: Design-For-Test Using Simulink and Stateflow (Hardcover)

INTRODUCTION

SIMULINK®: DYNAMIC SYSTEM SIMULATION FOR MATLAB®
Introduction
Creating a Model
Running a Simulation
Analyzing Simulation Results
Subsystems: Using Masks to Customize Blocks
Reference Blocks
Simulink Debugger

STATEFLOW®: CREATING FINITE STATE MACHINE MODELS
Introduction
Creating Charts
Entering a Stateflow Diagram
Defining Events and Data
Defining Stateflow Interfaces
Exploring and Searching
Debugging

FAULT MODELING AND SIMULATION
Fault Modeling
Fault Simulation

TESTABILITY ANALYSIS METHODS
Combinational Controllability and Observability Analysis Models
Sequential Controllability and Observability Analysis Models

THE AUTOMATIC TEST PATTERN GENERATION (ATPG) PROCESS
ATPG Fundamentals
Combinational Circuit ATPG (Current-Based ATPG Algorithms for Combinational Circuits)

TIMING VERIFICATION
Logical Determinant Theory
Digital Circuit Dynamics
Model Building for Timing Verification

SYSTEM AND EMBEDDED CORE TESTING
Introduction
Scan Path Architectures and Techniques
System and Embedded Core Testing

INDEX

References appear at the end of each chapter.