[eBook Code] Digital Electronics 3 (eBook Code, 1st)

Preface ix

Chapter 1. Synchronous Finite State Machines  1

1.1. Introduction  1

1.2. State diagram  2

1.3. Design of synchronous finite state machines  6

1.4. Examples  7

1.4.1. Flip-flops  7

1.4.2. Binary sequence detector 12

1.4.3. State machine implementation based on a state table 21

1.4.4. Variable width pulse generator  22

1.5. Equivalent states and minimization of the number of states  27

1.5.1. Implication table method 28

1.5.2. Partitioning method  37

1.5.3. Simplification of incompletely specified machines 42

1.6. State encoding 55

1.7. Transformation of Moore and Mealy state machines  61

1.8. Splitting finite state machines  63

1.8.1. Rules for splitting 63

1.8.2. Example 1 64

1.8.3. Example 2 67

1.9. Sequence detector implementation based on a programmable circuit  68

1.10. Practical considerations 70

1.10.1. Propagation delays and race conditions . 72

1.10.2. Timing specifications  74

1.11. Exercises 79

1.12. Solutions 97

Chapter 2. Algorithmic State Machines  169

2.1. Introduction  169

2.2. Structure of an ASM 169

2.3. ASM chart 170

2.4. Applications  175

2.4.1. Serial adder/subtracter  175

2.4.2. Multiplier based on addition and shift operations 183

2.4.3. Divider based on subtraction and shift operations 187

2.4.4. Controller for an automatic vending machine  189

2.4.5. Traffic light controller 193

2.5. Exercises  200

2.6. Solutions  205

Chapter 3. Asynchronous Finite State Machines  213

3.1. Introduction  213

3.2. Overview  214

3.3. Gated D latch  214

3.4. Muller C-element 218

3.5. Self-timed circuit 220

3.6. Encoding the states of an asynchronous state machine 224

3.7. Synthesis of asynchronous circuits  227

3.7.1. Oscillatory cycle  227

3.7.2. Essential and d-trio hazards 228

3.7.3. Design of asynchronous state machines 239

3.8. Application examples of asynchronous state machines  240

3.8.1. Pulse synchronizer 240

3.8.2. Asynchronous counter  243

3.9. Implementation of asynchronous machines using SR latches or C-elements 247

3.10. Asynchronous state machine operating in pulse mode  251

3.11. Asynchronous state machine operating in burst mode  256

3.12. Exercises 258

3.13. Solutions 266

Appendix. Overview of VHDL Language 287

A.1. Introduction  287

A.2. Principles of VHDL  287

A.2.1. Names 288

A.2.2. Comments 288

A.2.3. Library and packages 289

A.2.4. Ports  289

A.2.5. Signal and variable  289

A.2.6. Data types and objects  289

A.2.7. Attributes 290

A.2.8. Entity and architecture  291

A.3. Concurrent instructions  292

A.3.1. Concurrent instructions with selective assignment  293

A.3.2. Concurrent instructions with conditional assignment 293

A.4. Components  294

A.4.1. Generics  296

A.4.2. The GENERATE Instruction  296

A.4.3. Process 297

A.5. Sequential structures 298

A.5.1. The IF instruction 298

A.5.2. CASE instruction 303

A.6. Testbench 306

Bibliography 311

Index  313