Integrated Circuit Design for Radiation Environments (Hardcover)

· 제목 : Integrated Circuit Design for Radiation Environments (Hardcover) 
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전자공학 > 회로
· ISBN : 9781119966340
· 쪽수 : 392쪽
· 출판일 : 2019-12-31

Chapter 1 Introduction and Historical Perspective

1.1 Introduction

1.2 The Discovery of X-rays, Radiation and Subatomic Particles

1.3 The Nuclear Age

1.4 The Space Age

1.5 Semiconductors - Revolution, Evolution and Scaling

1.6 The Beginning of Ionizing Radiation Effects in Semiconductors

1.7 The Beginning of Single Event Effects in Semiconductors

1.8 Summary and Closing Comments

Chapter 2 Radiation Environments

2.1 Introduction

2.2 X-Rays, Gamma-Rays and the Atom

2.2.1 X-Rays

2.2.2 X-Ray Absorption

2.2.3 Auger Electrons

2.2.4 Nuclear Structure and Binding Energy

2.2.4.1 Models of the Nucleus

2.2.4.1.1 Liquid Drop Model

2.2.4.1.2 Fermi Gas Model

2.2.4.1.3 Shell Model

2.2.3.1.4 Other Nuclear Models

2.2.5 Alpha and Beta Decay

2.2.5.1 Alpha Decay

2.2.5.2 Beta Decay

2.2.6 Gamma-Ray Emission/Gamma Decay

2.2.7 Other Types of Nuclear Radiation

2.3 Natural Radioactivity

2.3.1 Exponential Decay

2.3.2 Decay series

2.4 The Space Environment

2.4.1 Solar Radiation

2.4.2 Trapped Radiation

2.4.3 Cosmic Rays

2.4.4 Atmospheric Neutrons

2.5 The Nuclear Reactor Environment

2.6 The Weapons Environment

2.7 The Environment in High-Energy Physics Facilities

2.8 Summary and Closing Comments

Chapter 3 Radiation Effects in Semiconductor Materials

3.1 Introduction

3.2 Basic Effects

3.2.1 Heavy Charged Particles

3.2.1.1 Stopping Power

3.2.1.2 Electronic Stopping

3.2.1.2.1 Q_max calculation

3.2.1.2.2 Bohr Analysis of Electronic Stopping

3.2.1.2.3 Bethe Formula

3.2.1.3 Nuclear stopping

3.2.2 Electrons

3.2.2.1 Electromagnetic radiation

3.2.2.2 Stopping Power

3.2.2.2.1 Collisional

3.2.2.2.2 Bremsstrahlung

3.2.2.2.3 Radiation length

3.2.2.2.4 Critical Energy

3.2.3 Neutrons

3.2.3.1 Neutron Cross Section

3.2.3.2 Interactions with matter

3.2.3.2.1 Elastic

3.2.3.2.2 Inelastic

3.2.3.2.3 Absorption

3.2.4 Photons (X-rays, Gamma Rays)

3.2.4.1 Photoelectric Effect

3.2.4.2 Compton Scattering

3.2.4.3 Pair Production

3.2.4.4 Photonuclear Reactions

3.3 Charge Trapping and Transport in Silicon Dioxide

3.3.1 Charge Generation/Recombination

3.3.2 Hole Trapping and Transport

3.3.2.1 E’ Centers

3.3.2.2 CTRW Model

3.3.3 The Silicon/Silicon Dioxide Interface

3.3.3.1 Interface Traps

3.3.3.2 Border Traps

3.3.3.3 Hydrogen

3.3.3.4 ELDRS

3.4 Bulk Damage

3.5 Summary and Closing Comments

Chapter 4 Radiation Induced Single Events

4.1 Introduction – Single Event Effects (SEE)

4.1.1 Single Event Upsets (SEU)

4.1.2 Multiple Bit Upset (MBU)

4.1.3 Single Event Transients (SET)

4.1.4 Single Event Functional Interrupts (SEFI)

4.1.5 Single Event Disturb (SED)

4.1.6 Single Event Snapback (SESB)

4.1.7 Single Event Latchup (SEL)

4.1.8 Single Event Burnout (SEB)

4.1.9 Single Event Gate Rupture (SEGR)

4.1.10 Single Event Hard Errors (SHE)

4.2 Single Event Upset (SEU)

4.2.1 SEU – Memory

4.2.2 SEU in CMOS Memory

4.2.3 SEU in Bipolar Memory

4.2.4 SEU in CMOS SRAM

4.2.5 SEU in Future Technology – FINFETs

4.3 Single Event Upset (SEU) – Particle Sources

4.3.1 SEU Source – Alpha Particles

4.3.2 SEU Source – Pions and Muons

4.3.3 SEU – Neutrons

4.3.4 SEU Source – Protons

4.3.5 SU – Heavy Ions

4.4 Single Event Gate Rupture (SEGR)

4.4.1 Definition SEGR

4.4.2 SEGR Source – Ion Track

4.4.3 SEGR Source – Failure Mechanism

4.4.4 SEGR – Modeling and Simulation

4.4.5 Power Transistors and SEGR

4.4.5.1 Lateral Power Transistors SEGR

4.4.5.2 Vertical MOS (VMOS) SEGR

4.4.5.3 Advanced Technologies – Planar MOSFET SEGR

4.4.5.3.1 Advanced Technology – FinFET SEGR

4.5 Single Event Transient (SET)

4.5.1 SET Definition

4.5.2 SET Source

4.5.3 SET Source – Failure Mechanisms

4.5.4 SET – Modeling and Simulation

4.5.5 SET in Integrated Circuits

4.5.5.1 Digital Circuitry

4.5.5.2 Continuous Time Analog Circuitry

4.5.6 Prediction and Hardening

4.6 Single Event Latchup (SEL)

4.6.1 SEL Definition

4.6.2 SEL Source

4.6.3 SEL Time Response

4.6.4 SEL Maximum Charge Collection Evaluation in a Parallelepiped Region

4.6.5 A SEL Design Practice

4.6.6 SEL Semiconductor Device Simulation

4.7 Summary and Closing Comments

Chapter 5 Radiation Testing

5.1 Introduction

5.1.1 Radiation Units and Measurements

5.2 Radiation Testing and Sources

5.2.1 Total Ionizing Dose (TID) Testing

5.2.2 Total Ionizing Dose (TID) Sources

5.2.3 Single-Event Effects (SEE) Testing

5.2.4 Single-Event Effects (SEE) Sources and Facilities

5.2.5 Neutron Testing

5.2.6 Neutron Sources

5.2.7 Proton Testing

5.2.8 Proton Sources

5.2.9 Transient Gamma Testing

5.2.10 Transient Gamma Sources

5.3 Summary and Closing Comments

Chapter 6 Device Modelling and Simulation Techniques

6.1 Introduction

6.2 Device Modeling

6.2.1 Circuit Simulators

6.2.2 Intrinsic Models

6.2.3 Composite Models and Inline Subcircuits

6.2.4 Analysis and Statistics Programs

6.3 Radiation Effects in Semiconductor Devices

6.3.1 MOS Capacitors and Transistors

6.3.1.1 MOS Capacitors

6.3.1.2 MOS Transistors

6.3.2 Diodes and Bipolar Transistors

6.3.2.1 Diodes

6.3.2.2 Bipolar Transistors

6.3.3 Power Devices

6.3.3.1 DMOS Composite Model

6.3.3.2 Operating Voltage

6.3.4 Other Devices

6.3.4.1 JFETS

6.3.4.2 Resistors

6.3.4.3 Capacitors

6.3.4 Some Modeling Challenges

6.4 Circuit simulation

6.4.1 Corner simulation

6.4.2 SEE Simulation

6.5 Summary and Closing Comments

Chapter 7 Semiconductor Process and Layout Techniques

7.1 Introduction

7.2 Substrate Hardened Technologies

7.2.1 Silicon on Insulator (SOI) Technologies

7.2.1.1 Separation by Implanted Oxygen (SIMOX)

7.2.1.2 Silicon Bonded (SIBOND)

7.2.2 Silicon on Sapphire (SOS)

7.2.3 Silicon on Diamond (SOD)

7.2.4 Silicon on Nothing (SON)

7.3 Oxide Hardening Technologies

7.3.1 Oxide Growth and Fluorination of Oxide

7.3.2 MOSFET Gate Oxide Hardening

7.3.3 Recessed Oxide (ROX) Hardening

7.3.4 LOCOS Isolation Hardening

7.3.5 Shallow Trench Isolation (STI) Hardening

7.4 CMOS Latchup Process Solutions

7.5 CMOS Substrates – High Resistance Substrates

7.5.1 50 Ω-cm Substrate Resistivity

7.6 Wells

7.6.1 Single Well – Diffused N-Well

7.6.2 Single Well – Retrograde N-Well

7.6.3 Dual-Well Technology

7.6.3.1 P-Well and P++ Substrate

7.6.3.2 P-Well and P+ Connecting Implant

7.7 Triple Well Technology

7.7.1 Triple Well – Full Separation of Wells

7.7.2 Triple Well – Merged Triple Well

7.7.3 Triple Well – Merged Triple Well with Blanket Implant

7.8 Sub-collectors

7.8.1 Epitaxial Grown Sub-collector

7.8.2 Implanted Sub-collector

7.8.3 Sub-collector – NPN and PNP Bipolar Current Gain

7.8.4 Sub-collector – Beta Product β_pnpβ_npn

7.9 Heavily Doped Buried Layers (HDBL)

7.9.1 Buried Implanted Layer for Lateral Isolation (BILLI) Process

7.9.2 Continuous HDBL Implant

7.9.3 Buried Guard Ring (BGR)

7.10 Isolation Concepts

7.10.1 LOCOS Isolation

7.10.2 Shallow Trench Isolation (STI)

7.10.3 Dual Depth Isolation

7.10.4 Trench Isolation (TI)

7.10.4.1 Trench Isolation (TI) and Sub-collector

7.11 Deep Trench

7.11.1 Deep Trench (DT) Within PNPN Structure

7.11.2 Deep Trench Structure and Sub-collector

7.11.3 Deep Trench Structure and Merged Triple Well

7.12 Layout Solutions

7.12.1 Polysilicon Bound Structures

7.12.2 Parasitic Isolation Device (PID)

7.13 Summary and Closing Comments

Chapter 8 Single Event Upset Circuit Solutions

8.1 Introduction

8.2 CMOS DRAM SEU Circuit Solutions

8.2.1 CMOS DRAM Redundancy

8.2.2 CMOS DRAM with SRAM Error Correction

8.3 CMOS SRAM SEU Circuit Solution

8.3.1 CMOS SRAM Four-Device Cell

8.3.2 CMOS SRAM Six Device Cell

8.3.3 CMOS SRAM Twelve Device Cell

8.4 Bipolar SRAM

8.4.1 Bipolar SRAM Cell with Resistor Loads

8.4.2 Bipolar SRAM Cell with Resistor Loads and Schottky Clamps

8.4.3 Bipolar SRAM Cell with PNP Transistors

8.5 Bipolar SRAM Circuit Solutions

8.6 SEU in CMOS Logic Circuitry

8.7 Summary and Closing Comments

Chapter 9 Latchup Circuit Solutions

9.1 Introduction

9.2 Power Supply Concepts

9.2.1 Power Supply Current Limit – Series Resistor

9.2.2 Power Supply Current Limit – Current Source

9.2.3 Power Supply Solutions – Voltage Regulator

9.2.4 Latchup Circuit Solutions – Power Supply De-Coupling

9.3 Overshoot and Undershoot Clamp Networks

9.3.1 Passive Clamp Networks

9.3.2 Active Clamp Networks

9.3.3 Dynamic Threshold Triple Well Passive and Active Clamp Networks

9.4 Passive and Active Guard Rings

9.4.1 Passive Guard Ring Circuits and Structures

9.4.2 Active Guard Ring Circuits and Structures

9.5 Triple Well Noise and Latchup Suppression Structures

9.6 System Level Latchup Issues

9.7 Summary and Closing Comments

Chapter 10 Emerging Effects and Future Technology

10.1 Introduction

10.2 Radiation Effects in Advanced Technologies

10.2.1 Moore’s Law, Scaling, and Radiation Effects

10.2.2 Technology Lifetime and Reliability

10.2.3 Terrestrial Issues

10.2.4 Space Mission Issues

10.2.5 Server Farms

10.2.6 Automotive

10.2.7 Internet of Things (IoT)

10.2.8 More than Moore

10.3 Radiation Effects in Semiconductor Nanostructures

10.3.1 Planar MOSFETs in Sub-25nm

10.3.2 Bulk FinFET

10.3.3 SOI FinFET

10.3.4 3-D Circuits

10.4 Radiation Effects and Advanced Packaging

10.4.1 Radiation Effects and 2.5-D Circuits and Technology

10.4.2 Radiation Effects and 3-D Circuits and Technology

10.4.3 More than More and 3-D Integration

10.5 Ruggedized Capability

10.5.1 Ruggedized Capability for Radiation

10.5.2 Ruggedized Capability for High Temperature

10.6 Radiation Models

10.7 A Nuclear World

10.8 Summary and Closing Comments