Model and Design of Bipolar and Mos Current-Mode Logic: CML, Ecl and Scl Digital Circuits (Hardcover, 2005)

Acknowledgment. Preface. 1. Devices Modeling for Digital Circuits. 1.1. PN JUNCTION. 1.1.1. Reverse Bias Condition. 1.1.2. Foward Bias Condition. 1.2. BIPOLAR-JUNCTION TRANSISTORS. 1.2.1 Basic Operation. 1.2.2. Early Effect or Base Width Modulation. 1.2.3. Charge Effects in the Bipolar Transistor. 1.2.4. Small Signal Model.1.3. MOS TRANSISTORS. 1.3.1. Basic Operation. 1.3.2. Triode or Linear Region. 1.3.3. Saturation or Active Region. 1.3.4. Body Effect. 1.3.5. p-channel Transistors. 1.3.6. Charge Effects in Saturation Region. 1.3.7 Charge Effects in Triode Region. 1.3.8. Charge Effects in Cutoff Region. 1.3.9. Small Signal Model. 1.3.10. Second Order Effects in MOSFET Modeling. 2. Current-Mode Digital Circuits. 2.1. The bipolar Current-mode inverter: basic principles. 2.2. The bipolar Current-mode inverter: Input-Output CharacteristicS and noise margin. 2.2.1. Differential input/output. 2.2.2. Single-ended input/output..2.2.3. Considerations on the non zero input current. 2.2.4. Remarks and comparison of differential/single-ended gates. 2.3. The buffered bipolar Current-mode (ECL) inverter. 2.4. The MOS Current-mode inverter. 2.4.1. Static modeling of the PMOS active load. 2.4.2. Input-output characteristics. 2.4.3. Evaluation of the noise margin. 2.4.4. Validation of the static model. . 2.4.5. The buffered MOS Current-Mode inverter and remarks. 2.5. Fundamental Current-mode logic gates. 2.5.1 Principle of operation of Current-Mode gates: the series gating concept. 2.5.2. Some examples of Current-Mode series gates. 2.5.3. Supply voltage limitations in bipolar Current-Mode gates. 2.5.4. MOS Current-Mode series gates and supply voltage limitations. 2.6. Typical applications of Current-mode circuits. 2.6.1. Radio Frequency applications. 2.6.2. Optic-fiber communications. 2.6.3. High-resolution mixed-signal ICs. 3. Methodologies for complex Current-mode logic gates. 3.1. BASIC CONCEPTS ON THE DESIGN OF A SERIESGATE. 3.1.1. Evaluation of function F(X1...Xn) implemented by a given topology. 3.1.2. Series-gate implementation of an assigned function F(X1...Xn). 3.1.3. Limitations of the general series-gate design approach. 3.2. A GRAPHICAL REDUCTION METHOD. 3.2.1. Basic concepts on the graphical approach in [CJ89]. 3.2.2. A design example. 3.3. an analytical formulation of the design strategy IN [CJ89]. 3.3.1. Analytical interpretation of CPE/NPE. 3.3.2. Analytical simplification through CPE/NPE: an example. 3.3.3. Circuit implementation of the simplified function after CPE-NPE. 3.4. A VEM-BASED REDUCTION METHOD. 3.5. INPUT ORDERING VERSUS DESIGN GOAL. 4. Modeling of Bipolar Current-mode gates. 4.1. Introduction to Modeling methodologies. 4.2. AN EFFICIENT APPROACH FOR CML GATES. 4.3. Simple modeling of THE CML inverter. 4.3.1. Accuracy of the CML simple model. 4.4. Accurate modeling of THE CML inverter. 4.4.1. Accuracy of the CML accurate model. 4.5. Simple AND ACCURATE modeling of THE ECL inverter. 4.5.1. Validation and improvement of the ECL model.4.6. SIMPLE modeling of bipolar CML MUX/XOR gates. 4.6.1. Validation of the MUX/XOR model. 4.6.2.Extension to the MUX/XOR when upper transistors switch. 4.7. ACCURATE modeling of bipolar CML MUX/XOR gates AND EXTENSION TO ECL GATES. 4.8. EVALUATION OF CML/ecl GATES INPUT CAPACITANCE. 4.9. bipolar Current-mode D Latch. 5. Optimized Design of Bipolar Current-mode gates. 5.1. Introduction to optimized methodology in cml gates. 5.2. OPTIMIZED DESIGN OF THE CML INVERTER. 5.2.1. Design with minimum transistor area. 5.2.2. Design with non-minimum transistor area. 5.2.3. Design examples. 5.3. OPTIMIZED DESIGN OF THE ECL INVERTER. 5.4. COMPARISON BETWEEN THE CML AND THE ECL INVERTER. 5.5. OPTIMIZED DESIGN OF BIPOLAR CURRENT-MODE MUX/XOR AND D LATCH. 5.5.1. Design of MUX/XOR CML gates with minimum transistor area. 5.5.2. Design of MUX/XOR CML gates with