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· 분류 : 외국도서 > 기술공학 > 기술공학 > 전자공학 > 반도체
· ISBN : 9781402071935
· 쪽수 : 229쪽
· 출판일 : 2002-09-30
목차
Preface. Acknowledgements. 1: Overview of IC Interconnects. 1.1. Silicon IC BEOL Technology Trends. 1.2. SIA Roadmap Interconnect Projections. 1.3. Low-kappa Requirements and Materials. 1.4. Need for Low-kappa CMP Process Understanding. 1.5. Summary. 1.6. References. 2: Low-kappa Interlevel Dielectrics. 2.1. Fluorinated Glasses. 2.2. Silsesquioxanes. 2.3. Organosilicate Glasses. 2.4. Polymers. 2.5. Fluorinated Hydrocarbons. 2.6. Nanoporous Silica Films. 2.7. Other Porous Materials. 2.8. References. 3: Chemical-Mechanical Planarization (CMP). 3.1. CMP Process Description. 3.2. CMP Processes with Copper Metallization. 3.3. CMP of Low-kappa Materials. 3.4. CMP Process Models. 3.5. Langmuir-Hinshelwood Surface Kinetics in CMP Modeling. 3.6. References. 4: CMP of BCB and SiLK Polymers. 4.1. Removal Rate in Copper Slurries. 4.2. Surface Roughness. 4.3. Surface and Bulk Film Chemistry. 4.4. Effect of Cure Conditions on BCB And SiLK Removal. 4.5. Effect of CMP and BCB and SiLK Film Hardness. 4.6. Comparison of BCB and SiLK CMP with Other Polymer CMP. 4.7. Summary. 4.8. References. 5: CMP of Organosilicate Glasses. 5.1. Surface Roughness. 5.3. Surface and Bulk Film Chemistry. 5.4. Copper Damascene Patterning with OSG Dielectrics. 5.5. Summary. 5.6. References. 6: Low-kappa CMP Model Based on Surface Kinetics. 6.1. Isolation of the Chemical Effects in SiLK CMP. 6.2. CMP with Simplified 'Model' SiLK Slurries. 6.3. Phenomenological Model for CMP Removal. 6.4. Five Step Removal Model Using Modified Langmuir-Hinshelwood Kinetics for SiLK CMP. 6.5. Two Step Removal Model Using Heterogeneous Catalysis for SiLK CMP. 6.6. Extendibility of Model to Describe the CMP of Other Materials. 6.7. References. 7: Copper CMP Model Based Upon Fluid Mechanics and Surface Kinetics. 7.1. Flow Model. 7.2. Copper Removal Model. 7.3. Model Results. 7.4. Copper CMP Experiments with Potassium Dichromate Based Slurry. 7.5. Summary. 7.6. References. 8: Future Directions in IC Interconnects and Related Low-&kgr; ILD Planarization Issues. 8.1. Planarization of Interconnects with Ultra Low-&kgr; ILDs. 8.2. Alternatives for the Post-Copper/Ultra Low-&kgr; Interconnect Era. 8.3. 3D Wafer-Scale Integration using Dielectric Bonding Glues and Inter-Wafer Interconnection with Copper Damascene Patterning. 8.4. Summary and Conclusions. 8.5. References. Appendices: A: Experimental Procedures and Techniques. B: XPS Depth-Profile Data. C: CMP Data for Anomalous SiLK Removal Behavior. Index.














