The Boundary Scan Handbook (Hardcover, 3, 2003)

1 Boundary-Scan Basics and Vocabulary.- 1.1 Digital Test Before Boundary-Scan.- 1.1.1 Edge-Connector Functional Testing.- 1.1.2 In-Circuit Testing.- 1.2 The Philosophy of 1149.1.- 1.3 Basic Architecture.- 1.3.1 The TAP Controller.- 1.3.2 The Instruction Register.- 1.3.3 Data Registers.- 1.3.4 The Boundary Register.- 1.3.5 Optimizing a Boundary Register Cell Design.- 1.3.6 Architecture Summary.- 1.3.7 Field-Programmable IC Devices.- 1.3.8 Boundary-Scan Chains.- 1.4 Non-Invasive Operational Modes.- 1.4.1 BYPASS.- 1.4.2 IDCODE.- 1.4.3 USERCODE.- 1.4.4 SAMPLE.- 1.4.5 PRELOAD.- 1.5 Pin-Permission Operational Modes.- 1.5.1 EXTEST.- 1.5.2 INTEST.- 1.5.3 RUNBIST.- 1.5.4 HIGHZ.- 1.5.5 CLAMP.- 1.5.6 Exceptions Due to Clocking.- 1.6 Extensibility.- 1.7 Subordination of IEEE 1149.1.- 1.8 Costs and Benefits.- 1.8.1 Costs.- 1.8.2 Benefits.- 1.8.3 Trends.- 1.9 Other Testability Standards.- 2 Boundary-Scan Description Language (BSDL).- 2.1 The Scope of BSDL.- 2.1.1 Testing.- 2.1.2 Compliance Assurance.- 2.1.3 Synthesis.- 2.2 Structure of BSDL.- 2.3 Entity Descriptions.- 2.3.1 Generic Parameter.- 2.3.2 Logical Port Description.- 2.3.3 Standard USE Statement.- 2.3.4 Use Statements.- 2.3.5 Component Conformance Statement.- 2.3.6 Device Package Pin Mappings.- 2.3.7 Grouped Port Identification.- 2.3.8 TAP Port Identification.- 2.3.9 Compliance Enable Description.- 2.3.10 Instruction Register Description.- 2.3.11 Optional Register Description.- 2.3.12 Register Access Description.- 2.3.13 Boundary-Scan Register Description.- 2.3.14 RUNBIST Execution Description.- 2.3.15 INTEST Execution Description.- 2.3.16 User Extensions to BSDL.- 2.3.17 Design Warnings.- 2.4 Some advanced BSDL Topics.- 2.4.1 Merged Cells.- 2.4.2 Asymmetrical Drivers.- 2.5 BSDL Description of 74BCT8374.- 2.6 Packages and Package Bodies.- 2.6.1 STD_1149_1_2001.- 2.6.2 Cell Description Constants.- 2.6.3 Basic Cell Definitions BCO to BC7.- 2.6.4 Cells BC_8 to BC_10 Introduced in 2001.- 2.6.5 User-Defined Boundary Cells.- 2.6.6 Definition of BSDL Extensions.- 2.7 Writing BSDL.- 2.8 Summary.- 3 Boundary-Scan Testing.- 3.1 Basic Boundary-Scan Testing.- 3.1.1 The 1149.1 Scanning Sequence.- 3.1.2 Basic Test Algorithm.- 3.1.3 The "Personal Tester" Versus ATE.- 3.1.4 In-Circuit Boundary-Scan.- 3.1.5 IC Test.- 3.1.6 ICBIST.- 3.2 Testing with Boundary-Scan Chains.- 3.2.1 1149.1 Chain Integrity.- 3.2.2 Interconnect Test.- 3.2.3 Connection Tests.- 3.2.4 Interaction Tests.- 3.2.5 BIST and Custom Tests.- 3.3 Porting Boundary-Scan Tests.- 3.4 Boundary-Scan Test Coverage.- 3.5 Summary.- 4 Advanced Boundary-Scan Topics.- 4.1 DC Parametric IC Tests.- 4.2 Sample Mode Tests.- 4.3 Concurrent Monitoring.- 4.4 Non-Scan IC Testing.- 4.5 Non-Digital Device Testing.- 4.6 Mixed Digital/Analog Testing.- 4.7 Multi-Chip Module Testing.- 4.8 Firmware Development Support.- 4.9 In-System Configuration.- 4.10 Flash Programming.- 4.11 Hardware Fault Insertion.- 4.12 Power Pin Testing.- 5 Design for Boundary-Scan Test.- 5.1 Integrated Circuit Level DFT.- 5.1.1 TAP Pin Placement.- 5.1.2 Power and Ground Distribution.- 5.1.3 Instruction Capture Pattern.- 5.1.4 Damage Resistant Drivers.- 5.1.5 Output Pins.- 5.1.6 Bidirectional Pins.- 5.1.7 Post-Lobotomy Behavior.- 5.1.8 IDCODEs.- 5.1.9 User-Defined Instructions.- 5.1.10 Creation and Verification of BSDL.- 5.2 Board-Level DFT.- 5.2.1 Chain Configurations.- 5.2.2 TCK/TMS Distribution.- 5.2.3 Mixed Logic Families.- 5.2.4 Board Level Conflicts.- 5.2.5 Control of Critical Nodes.- 5.2.6 Power Distribution.- 5.2.7 Boundary-Scan Masters.- 5.2.8 Post-Lobotomy Board Behavior.- 5.3 System-Level DFT.- 5.3.1 The MultiDrop Problem.- 5.3.2 Coordination with Other Standards.- 5.4 Summary.- 6 Analog Measurement Basics.- 6.1 Analog In-Circuit Testing.- 6.1.1 Analog Failures.- 6.1.2 Measuring an Impedance.- 6.1.3 Errors and Corrections.- 6.1.4 Measurement Hardware.- 6.2 Limited Access Testing.- 6.2.1 Node Voltage Analysis.- 6.2.2 Testing With Node Voltages.- 6.2.3 Limited Access