Optimal VLSI Architectural Synthesis: Area, Performance and Testability (Paperback, 1992)

I: Introduction.- 1. Global VLSI Design Cycle.- 1.1 VLSI Design Cycle.- 1.2 Hybrid Systems Design.- 1.3 Impact Of Technologies.- 1.4 Test Considerations.- 1.5 Bottlenecks and Open Issues.- 1.6 focus of Text.- 2. Behavioral and Structural Interfaces.- 2.1 Input to an Architectural Synthesizer.- 2.2 Interface Primitives for External Processes.- 2.3 Output Primitives from an Architectural Synthesizer.- II: Review And Background.- 3. State of the Art Synthesis.- 3.1 Terminology and Subtask Definitions.- 3.2 High Level Transformations.- 3.3 Independent Subtask Optimization.- 3.3.1 Scheduling.- 3.3.2 Resource Allocation.- 3.4 Iterative and Simultaneous Approaches.- 3.5 Mathematical Approaches.- 3.5.1 Branch and Bound.- 3.5.2 Simulated Annealing.- 3.5.3 Makespan Scheduling.- 3.5.4 Feasibility Models.- 3.6 Timing Constrained Synthesis.- 3.7 Cost Functions for Design Evaluation.- 4. Introduction to Integer Programming.- 4.1 Applications and Models.- 4.2 Solution of Unstructured IPs.- 4.3 Polyhedral Approaches To Solving Ips.- 4.4 The Node Packing Problem.- 4.5 The Knapsack Problem.- III: Optimal Architectural Synthesis With Interfaces.- 5. A Methodology for Architectural Synthesis.- 5.1 Requirements for High Level Synthesis Tools.- 5.2 High Level Methodology.- 5.3 OASIC Methodology.- 5.4 An Introduction to OASIC.- 5.5 Oasic Terminology, Assumptions, and Preprocessing.- 5.5.1 terminology.- 5.5.2 Assumptions.- 5.5.3 Preprocessing.- 6. Simultaneous Scheduling, and Selection and Allocation Of Functional Units.- 6.1 The Formal Model.- 6.2 Cost Functions.- 6.3 Functional Unit Type Selection.- 7. Oasic: Area-Delay Constrained Architectural Synthesis.- 7.1 The Precedence Constrained Scheduling Model.- 7.2 Functional Unit Allocation.- 7.3 Register Allocation.- 7.4 Bus Allocation.- 7.5 Cost Functions.- 7.6 Application Specific Tightening of Con-straints.- 8. Support for Algorithmic Constructs.- 8.1 Conditional Code.- 8.2 Loops.- 8.3 Functional Pipelining.- 9. Interface Constraints.- 9.1 General Interface: Minimum and Max-imum Timing Constraints.- 9.2 Analog Interface: Fixed Timing Con-straint.- 9.3 Asynchronous Interface.- 9.4 Unknown Unbounded Delays.- 9.5 Complex Timing Constraints.- 10. Oasic Synthesis Results.- 10.1 Elliptical Wave Filter.- 10.1.1 Structured Model.- 10.1.2 Area-delay Optimized.- 10.2 Neural Network Algorithm.- 10.3 Conditional Code Example.- 10.4 Analog and Asynchronous interface Examples.- 10.6.1 Analog Interface.- 10.6.2 Asynchronous Interface.- IV: Testable Architectural Synthesis.- 11. Testability in Architectural Synthesis.- 11.1 Design and Test.- 11.1.1 Choices in Design and Test.- 11.2 Approaches to Testability.- 11.2.1 Test Measures and Tools.- 11.2.2 Design Modifications for Testability.- 11.3 Previous Research in Design for Test.- 11.4 Approaches To Test With Synthesis.- 11.4.1 Previous Research.- 11.4.2 Commercial Systems.- 11.5 Inadequacies of Current Synthesis With Test.- 11.5.1 Feedback.- 11.5.2 Integration.- 11.5.3 Constraint Estimation.- 12. The Catree Architectural Synthesis With Testability.- 12.1 problem description.- 12.2 Comparison With Previous Research.- 12.3 Two Synthesis With Test Methodologies:Catree & Catree2.- 12.4 Catree Design Synthesis Stages.- 12.4.1 Input Specification.- 12.4.2 Design Allocation.- 12.4.3 Catree Area and Delay Estimates.- 12.4.4 Test Incorporation.- 12.4.5 Feedback.- 12.5 Catree Synthesis Results.- 12.6 Catree Discussion.- 12.7 Catree2 Design Synthesis stages.- 12.7.1 Tree Formation and Functional Unit Binding.- 12.7.2 Test Incorporation.- 12.7.3 (Test) Register and Bus Binding.- 12.7.4 Feedback.- 12.8 Catree2 Experiments.- 12.9 Catree2 Discussion.- V: Summary and Future Research.- 13. Summary and Future Research.- 13.1 Oasic Summary.- 13.2 Catree Summary.- 13.3 Future Extensions.- 13.4 Concluding Remarks.- References.