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· 분류 : 외국도서 > 기술공학 > 기술공학 > 나노테크놀리지/MEMS
· ISBN : 9781466564268
· 쪽수 : 408쪽
· 출판일 : 2014-02-20
목차
Introduction
Introduction
Characterization of Technology Scaling
Analog Design Challenges in Scaled CMOS Technology
Motivation for CAD Techniques
Conventional Design Techniques for Analog IC Design
Knowledge-based CAD Technique for Analog ICs
Summary and Conclusion
High-Level Modeling and Design Techniques
Introduction
High-Level Model
Behavioral Model Generation Technique
Introduction to Optimization Techniques
Some Important Optimization Algorithms
Multi-Objective Optimization Method
Pareto Optimal Front
Design Space Exploration
Computational Complexity of a CAD Algorithm
Technology aware Computer Aided IC Design Technique
Commercial Design Tools
Modeling of Scaled MOS Transistor for VLSI Circuit Simulation
Introduction
Device Modeling
Compact Models
Long-Channel MOS Transistor
Threshold Voltage Model for Long-channel Transistor with Uniform Doping
SPICE Level Drain Current Model
SPICE Level I-V Model
MOSFET Capacitances
Short-Channel MOS Transistor
Threshold Voltage for Short-Channel MOS Transistor
I-V Model for Short-Channel MOS transistor
Weak Inversion Characteristics of a Scaled MOS transistor
Hot Carrier Effect
Source-Drain Resistance Model
Compact Modeling
Salicide Technology
Physical Model for Output Resistance
Poly-silicon Gate Depletion Effect
Effective Channel Length and Width
Summary and Conclusion
Performance and Feasibility Model Generation using Learning based Approach
Introduction
Requirement of Leaning-based Approaches
Regression Problem for Performance Model Generation
Some Related Works
Preliminaries on Artificial Neural Network
Neural Network Model Development
Case Study 1: Performance Modeling of CMOS Inverter
Case Study 2: Performance Modeling of Spiral Inductor
Dynamic Adaptive Sampling
Introduction to Least Squares Support Vector Machines
Feasible Design Space and Feasibility Model
Case Study 3: Combined Feasibility and Performance Modeling of Two-Stage Operational Amplifier
Case Study 4: Architecture-Level Performance Modeling of Analog Systems
Meet-in-the-Middle Approach for Construction of Architecture-Level Feasible Design Space
Case Study 5: Construction of FeasibilityModel at Architecturelevel of an Interface Electronics for MEMS Capacitive Accelerometer System
Summary and Conclusion
Circuit Sizing and Specification Translation
Introduction
Circuit Sizing as a Design Space Exploration Problem
Particle Swarm Optimization Algorithm (PSO)
Case Study 1: Design of a Two Stage Miller OTA
Case Study 2: Synthesis of On-chip Spiral Inductors
Case Study 3: Design of a nano-scale CMOS inverter for Symmetric Switching Characteristics
The gm/ID Methodology for Low Power Design
High-Level Specification Translation
Summary and Conclusion
Advanced Effects of Scaled MOS Transistors
Introduction
Narrow Width Effect on Threshold Voltage
Channel Engineering of MOS Transistor
Gate Leakage Current
High-κ Dielectrics and Metal-Gate/High-κ CMOS Technology
Advanced Device Structures of MOS Transistors
Noise Characterization of MOS Transistors
Gate Resistance and Substrate Network Model of MOS Transistor for RF Applications
Summary and Conclusion
Process Variability and Reliability of Nano-scale CMOS Analog Circuits
Introduction
Basic Concepts on Yield and Reliability
Sources of Variations in Nanometer Scale Technology
Systematic Process Variations
Random Process Variations
Statistical Modeling
Physical Phenomena Affecting the Reliability of Scaled MOS
Transistor
Physical Model for MOSFET Degradation due to HCI
Reaction-Diffusion Model for NBTI
Reliability Simulation for Analog Circuits
Summary and Conclusion
Bibliography
