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· 제목 : A Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Systems (Paperback)
· 분류 : 외국도서 > 컴퓨터 > 하드웨어 > 일반
· ISBN : 9781484263501
· 쪽수 : 319쪽
· 출판일 : 2022-09-15
· 분류 : 외국도서 > 컴퓨터 > 하드웨어 > 일반
· ISBN : 9781484263501
· 쪽수 : 319쪽
· 출판일 : 2022-09-15
목차
Chapter 1: Introduction
Chapter Goal: Verilog-A delineation. Comparison to other HDLs and modeling languages. Book organization.
Chapter 2: The Lexical Basis of Verilog-A
Chapter Goal: Introducing Verilog-A lexical tokens, token separators as well as basic token groups and token containers.
Chapter 3: Basic Types and Expressions
Chapter Goal: Introducing integer, real and string data types and how expressions are assembled for different types using operators.
Chapter 4: Nets and Signals
Chapter Goal: Introducing the concept of nets and signals defined by nature and net_discipline types.
Chapter 5: Modules and Netlists
Chapter Goal: Introducing modules, as basic units of hierarchy in Verilog-A language, and their instantiation in SPICE and Verilog-A netlists.
Chapter 6: Parameters and Paramsets
Chapter Goal: Introducing the concept of parameters, customization of modules by passing parameters into a module at instantiation and the concept of instance and model parameters defined via paramsets.
Chapter Goal: Introducing the concept of analog branch assignments and signal access mechanisms.
Chapter 8: Procedural Statements
Chapter Goal: Introducing analog procedural block and procedural control statements.
Chapter 9: Derivative and Integral Operators
Chapter Goal: Detailed description of analog functions used to perform differentiation and integration in time.
Chapter 10: Built-in Mathematical Functions
Chapter Goal: Define all Verilog-A standard mathematical function.
Chapter 11: User Defined Functions
Chapter Goal: Describe how to write modular, maintainable and reusable models in Verilog-A using user defined functions.
Chapter 12: Analog Filter Functions
Chapter Goal: Introducing Verilog-A time and frequency domain filter functions and their usage with constant and dynamic arguments.
Chapter 13: Look-Up Table Models
Chapter Goal: Describing how to create a multidimensional interpolation lookup-up table models in Verilog-A
Chapter 14: Small Signal and Noise Sources
Chapter Goal: Introducing Verilog-A functions supporting small signal and noise analysis in SPICE simulators.
Chapter 15: Events
Chapter Goal: Introducing methods to control analog behaviour of the component models in Verilog-A.
Chapter 16: Input and Output
Chapter Goal: Describe methods and functions to read and write formatted data.
Chapter 17: Simulator Query and Control Methods
Chapter Goal: Describing the methods to access the simulator kernel parameters in the Verilog-A model.
Chapter 18: Attributes
Chapter Goal: Introducing attributes as a mechanism for specifying properties about objects, statements and groups of statements in the Verilog-A source that can be used by the simulator.
Chapter 19: Compiler Directives
Chapter Goal: Introducing compiler directives that dictate Verilog-A compiler behaviour in a pre-processing
compilation phase.Chapter 20: SPICE Compatibility
Chapter Goal: Describes the degree of compatibility with SPICE-like simulators which Verilog-A provides and the approach taken to provide that compatibility.
