Digital VLSI Design with Verilog: A Textbook from Silicon Valley Polytechnic Institute (Hardcover, 2, 2014)

Introduction.- Verilog vectors.- Logical (Boolean) Operators.- Bitwise Operators: Vectors and Reduction.- VCD File Dump.- SDF File Dump.- More Language Constructs.- Procedural Control.- Net Types, Simulation, & Scan.- PLLs and the Ser Des Project.- Date Storage and Verilog Arrays.- Counter Types and Structures.- Contention and Operator Precedence.- Digital Basics: Three-State Buffer and Decoder.- Back to the PLL and the Ser Des.- State Machine and FIFO Design.- Rise-Fall Delays and Event Scheduling.- Built-in Gates and Net Types.- Procedural Control and Concurrency.- Hierarchical Names and generate Blocks.- Serial-Parallel Conversion.- UDPs, Timing Triplets, and Switch-level Models.- Parameter Types and Module Connection.- Hierarchical Names and Design Partitions.- Verilog Configurations.- Timing Arcs and specify Delays.- Timing Checks and Pulse Controls.- The Sequential Deserializer.- PLL Redesign.- The Concurrent Deserializer.- The Serializer and the SerDes.- Design For Test(DFT).- DFT for a Full-Duplex SerDes.- SDF Back-Annotation.- Wrap-up: TheVerilog Language.- Deep-Submicron Problems and Verification.- System Verilog.- Verilog-AMS.