Evolvable Systems: From Biology to Hardware: Third International Conference, Ices 2000, Edinburgh, Scotland, UK, April 17-19, 2000 Proceedings (Paperback, 2000)

Automatic Synthesis, Placement, and Routing of an Amplifier Circuit by Means of Genetic Programming.- Immunotronics : Hardware Fault Tolerance Inspired by the Immune System.- Ant Colony System for the Design of Combinational Logic Circuits.- Evolving Cellular Automata for Self-Testing Hardware.- Dynamic Optimisation of Non-linear Feed-Forward Circuits.- From the Sea to the Sidewalk: The Evolution of Hexapod Walking Gaits by a Genetic Algorithm.- Experiments in Evolvable Filter Design using Pulse Based Programmable Analogue VLSI Models.- The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic.- Evolution of Controllers from a High-Level Simulator to a High DOF Robot.- The Evolution of 3-d C.A. to Perform a Collective Behavior Task.- Initial Evaluation of an Evolvable Microwave Circuit.- Towards an Artificial Pinna for a Narrow-Band Biomimetic Sonarhead.- Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array.- Understanding Inherent Qualities of Evolved Circuits: Evolutionary History as a Predictor of Fault Tolerance.- Comparison between Three Heuristic Algorithms to Repair a Large-Scale MIMD Computer.- A Hardware Implementation of an Embryonic Architecture Using Virtex® FPGAs.- Everything on the Chip: A Hardware-Based Self-Contained Spatially-Structured Genetic Algorithm for Signal Processing.- Evolutionary Techniques in Physical Robotics.- Biology Meets Electronics: the Path to a Bio-Inspired FPGA.- The Design and Implementation of Custom Architectures for Evolvable Hardware Using Off-the-Shelf Programmable Devices.- Mixtrinsic Evolution.- Evolution of Robustness in an Electronics Design.- Circuit Evolution and Visualisation.- Evolutionary Robots with Fast Adaptive Behavior in New Environments.- The Advantages of Landscape Neutrality in Digital Circuit Evolution.- Genetic Algorithm-Based Design Methodology for Pattern Recognition Hardware.- A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution.