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· 제목 : Verification and Validation in Systems Engineering: Assessing UML/SysML Design Models (Hardcover) 
· 분류 : 외국도서 > 컴퓨터 > 소프트웨어 개발/엔지니어링 > 시스템 분석/설계
· ISBN : 9783642152276
· 쪽수 : 248쪽
· 출판일 : 2010-11-18
· 분류 : 외국도서 > 컴퓨터 > 소프트웨어 개발/엔지니어링 > 시스템 분석/설계
· ISBN : 9783642152276
· 쪽수 : 248쪽
· 출판일 : 2010-11-18
목차
Architecture Frameworks, Model-Driven Architecture, and Simulation.- Unified Modeling Language.- Systems Modeling Language.- Verification, Validation, and Accreditation.- Automatic Approach for Synergistic Verification and Validation.- Software Engineering Metrics in the Context of Systems Engineering.- Verification and Validation of UML Behavioral Diagrams.- Probabilistic Model Checking of SysML Activity Diagrams.- Performance Analysis of Time-Constrained SysML Activity Diagrams.- Semantic Foundations of SysML Activity Diagrams.- Soundness of the Translation Algorithm.- Conclusion.
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