60-ghz Cmos Phase-locked Loops (Paperback)

1 Introduction. 2 Synthesizer system architecture; 2.1 IEEE 802.15.3c channelization; 2.2 60 GHz frequency conversion techniques; 2.3 Proposed PLL architecture - flexible, reusable, multi-frequency; 2.4 System analysis and design; 2.5 System simulations; 2.6 Target specifications; 2.7 Summary. 3 Layout and measurements at mm-wave frequencies; 3.1 Layout problems and solutions; 3.2 Measurement setups; 3.3 Conclusions.- 4 Design of high frequency components; 4.1 Prescaler; 4.2 Voltage Controlled Oscillator; 4.3 Synthesizer front-ends; 4.4 Conclusions.- 5 Design of low frequency components; 5.1 Feedback division; 5.2 Phase-frequency detector, charge-pump and loop filter; 5.3 Conclusions.- 6 Synthesizer integration; 6.1 Synthesizer for 60 GHz sliding-IF frequency conversion; 6.2 Synthesizer with down-conversion mixer in feedback loop; 6.3 Dual-mode synthesizer; 6.4 Conclusions.- 7 Conclusions.- Appendix. References.