Advanced Hdl Synthesis and Soc Prototyping: Rtl Design Using Verilog

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· 제목 : Advanced Hdl Synthesis and Soc Prototyping: Rtl Design Using Verilog (Hardcover, 2019)
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전자공학 > 회로
· ISBN : 9789811087752
· 쪽수 : 307쪽
· 출판일 : 2019-01-18

Introduction.- SOC Design.- RTL Design Guidelines.- RTL Design and Verification.- Processor cores and Architecture design.- Buses and protocols in SOC designs.- DSP Algorithms and Video Processing.- ASIC and FPGA Synthesis.- Static Timing Analysis.- SOC Prototyping.- SOC Prototyping guidelines.- Design Integration and SOC synthesis.- Interconnect delays and Timing.- SOC Prototyping and debug techniques.- Testing at the board level.