Logic Synthesis and Soc Prototyping: Rtl Design Using VHDL (Paperback, 2020)

Introduction.- ASIC Design and SOC prototype.- Design using VHDL & Guidelines.- Design using VHDL & Guidelines.- Design and Verification Strategies.- VHDL Design and RTL Tweaks.- ASIC Synthesis and Design Constraints.- Design optimization.- Design optimization.- FPGA for SOC Prototype.- Prototype using Single and Multiple FPGA.