책 이미지
eBook 미리보기
책 정보
· 제목 : Recent Advances in Pmos Negative Bias Temperature Instability: Characterization and Modeling of Device Architecture, Material and Process Impact (Hardcover, 2022)
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전자공학 > 회로
· ISBN : 9789811661198
· 쪽수 : 311쪽
· 출판일 : 2021-11-26
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전자공학 > 회로
· ISBN : 9789811661198
· 쪽수 : 311쪽
· 출판일 : 2021-11-26
목차
1. Basic features, process dependence and variability of NBTI in p-MOSFETs
1.1. Introduction
1.2. Measurement of NBTI kinetics
1.2.1. Ultra-fast measure-stress-measure method
1.2.2. Time evolution of stress and recovery
1.2.3. Impact of measurement delay
1.2.4. Voltage and temperature dependence
1.2.5. Duty cycle and frequency dependence
1.2.6. Empirical estimation of end-of-life degradation
1.3. Overview of NBTI process dependence
1.3.1. Impact of SiGe channel
1.3.2. Impact of Nitrogen
1.3.3. Impact of gate stack thickness scaling
1.3.4. Impact of fin dimension scaling
1.3.5. Impact of layout
1.4. NBTI in small area devices
1.4.1. Stress and recovery kinetics
1.4.2. Distribution of degradation
1.4.3. Correlation of variability and variable NBTI
1.4.4. Random Telegraph Noise
1.5. Physical mechanism of NBTI ? an overview
1.6. Summary
2. NBTI kinetics modeling framework
2.1. Introduction
2.2. Overview of NBTI modeling framework
2.3. Generation and passivation of interface traps
2.3.1. Double interface Reaction-Diffusion (RD) model
2.3.2. Physical mechanism of defect depassivation
2.3.3. A discussion on RD model parameters
2.3.4. DCIV measurement method
2.3.5. Prediction of DCIV data
2.3.6. Analysis of Ge% and N% impact
2.3.7. Comparison of continuum and stochastic frameworks
2.4. Occupancy of generated interface traps
2.4.1. Transient Trap Occupancy Model (TTOM)
2.4.2. Validation of TTOM framework2.5. Hole trapping in pre-existing bulk traps
2.6. Validation of TTOM enabled RD and hole trapping
2.7. Time Dependent Defect Spectroscopy (TDDS) analysis
2.8. Generation of bulk traps
2.9. Validation of TTOM enabled RD and bulk trap generation
2.10. Summary
3. Modeling of NBTI kinetics in HKMG Si and Si-capped SiGe p-MOSFETs
3.1. Introduction
3.2. Description of process splits
3.3. Analysis of Gate First HKMG planar devices
3.3.1. DC stress and recovery kinetics
3.3.2. Impact of measurement delay
3.3.3. Nitrogen impact on NBTI parameters
3.3.4. AC stress kinetics
3.4. Analysis of mean stress-recovery kinetics from small area devices
3.5. Process dependence of model parameters
3.6. Estimation of end-of-life degradation
3.6.1. Calculation by empirical method
3.6.2. Calculation by physical model
3.6.3. Comparison of empirical and physical methods
3.7. Analysis of Si-capped SiGe planar devices
3.7.1. Stress and recovery kinetics
3.7.2. Voltage acceleration factor
3.7.3. Process dependence of model parameters
3.7.4. Estimation of end-of-life degradation
3.8. Summary
4. Modeling of NBTI kinetics in HKMG Si and SiGe FDSOI MOSFETs
4.1. Introduction
4.2. Description of process splits
4.3. Analysis of measured data
4.3.1. Time kinetics of stress and recovery
4.3.2. Impact of Ge% and N%
4.3.3. Impact of layout (STI to active spacing)
4.3.4. Process dependence of model parameters
4.4. Explanation of process dependence
4.4.1. Impact of Ge% and N%
4.4.2. Impact of layout effect
4.5. Estimation of end-of-life degradation
4.6. Summary
5. Modeling of NBTI kinetics in RMG HKMG Si FinFETs
5.1. Introduction
5.2. Description of process splits
5.3. Analysis of measured data 5.3.1. DC stress and recovery kinetics
5.3.2. Voltage and temperature dependence
5.3.3. AC stress and recovery kinetics
5.3.4. Duty cycle and frequency dependence
5.4. Comparison of FinFET architectures
5.4.1. DC stress and recovery kinetics
5.4.2. Voltage and temperature dependence
5.4.3. AC stress and recovery kinetics
5.4.4. Duty cycle and frequency dependence
5.5. Analysis of fin (channel) length scaling
5.6. Analysis of mean stress-recovery kinetics from small area devices
5.7. Process and dimension dependence of model parameters
5.8. Analysis of end-of-life degradation
5.8.1. Comparison of empirical and physical methods
5.8.2. Impact of device architecture
5.9. Summary
6. Modeling of NBTI kinetics in RMG HKMG Si and SiGe bulk FinFETs
6.1. Introduction
6.2. Description of process splits
6.3. Analysis of measured data ? impact of Ge% and N%
6.3.1. DC stress and recovery kinetics
6.3.2. AC stress and recovery kinetics
6.3.3. Voltage and temperature dependence ? DC stress
6.3.4. Voltage and temperature dependence ? AC stress
6.3.5. Frequency and duty cycle dependence
6.3.6. Anomalous frequency dependence
6.4. Analysis of fin (channel) length and width scaling
6.5. Explanation of process dependence
6.5.1. Process dependence of model parameters
6.5.2. Explanation of material (Ge%, N%) dependence6.5.3. Similarity of FDSOI and FinFET parameters
6.5.4. Explanation of dimension scaling
6.6. Analysis of end-of-life degradation
6.6.1. Contribution of different subcomponents
6.6.2. Comparison of empirical and physical methods6.7. Summary
7. TCAD implementation of NBTI framework
7.1. Introduction
7.2. Implementation in TCAD framework
7.2.1. General overview
7.2.2. Process simulation
7.2.3. Bandstructure calculation and model parameter extraction
7.2.4. Device simulation ? MSC framework
7.2.5. Device simulation ? CE depassivation model
7.2.6. Transient Trap Occupancy Model
7.3. Impact of physical models
7.3.1. Quantum potential
7.3.2. Mechanical strain
7.4. Validation using experimental data
7.4.1. Impact of Ge% in channel
7.4.2. Impact of fin (channel) length scaling
7.4.3. Impact of fin (channel) width scaling
7.5. Prediction of technology scaling
7.6. Summary
8. NBTI in small area devices
8.1. Introduction
8.2. Experimental results
8.2.1. Stress and recovery kinetics
8.2.2. Distribution of statistical degradation
8.2.3. Time Dependent Defect Spectroscopy
8.2.4. Impact of single charge
8.3. Stochastic NBTI modeling framework
8.3.1. Generation and passivation of interface traps
8.3.2. Impact of H2 lock in
8.3.3. Occupancy of interface traps
8.3.4. Hole trapping in pre-existing traps
8.3.5. Calculation of percolation effect and charge impact
8.4. Comparison of stochastic and continuum models
8.5. Prediction of experimental data
8.6. Summary 9. Analysis of digital logic circuit degradation
9.1. Introduction
9.2. Explanation of simulation flow
9.2.1. Implementation in TCAD framework
9.2.2. Implementation in SPICE framework
9.3. Comparison of TCAD and SPICE platforms
9.4. Analysis of RO degradation
9.5. Characterization of standard cells
9.6. Estimation of circuit degradation (DC worst case)
9.6.1. Conventional analysis scheme
9.6.2. Impact of subthreshold slope degradation
9.7. Impact of gate activity
9.7.1. Compact model description
9.7.2. Analysis of random input patterns
9.7.3. Effective duty simulation
9.7.4. Verification of effective duty approach
9.8. Summary
10. Statistical analysis of SRAM degradation
10.1. Introduction
10.2. Statistical compact NBTI model
10.3. Monte Carlo SPICE simulation setup
10.4. Estimation of SRAM parameter degradation
10.4.1. Read SNM
10.4.2. Hold SNM
10.4.3. Flip time
10.5. Analysis of high density and high speed cells
10.6. Impact of bit activity
10.7. Impact of time-zero and BTI correlation
10.8. Impact of subthreshold slope degradation
10.9. Summary
