ASIC Design and Synthesis: Rtl Design Using Verilog (Hardcover, 2021)

· 제목 : ASIC Design and Synthesis: Rtl Design Using Verilog (Hardcover, 2021) 
· 분류 : 외국도서 > 기술공학 > 기술공학 > 전자공학 > 회로
· ISBN : 9789813346413
· 쪽수 : 330쪽
· 출판일 : 2021-01-07

1. Introduction

a. ASICs

b. History and evolutions

c. Types of ASIC

d. ASIC Vs programmable ASICs

e. ASIC design flow

f. Programmable ASIC Design flow

g. Applications of ASIC

2. Design using CMOS

a. CMOS basic concepts

b. Process nodes

c. Combinational logic design using CMOS

d. Sequential logic design using CMOS

e. Memories

f. Registers

g. Clock generators

3. ASIC design synthesis for combinational design (RTL using VHDL)

a. Multiplexers

b. Demultiplexers

c. Encoders

d. Priority encoders

e. Adders/subtractors

f. Multipliers

g. Code converters

4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL)

a. ALU

b. Barrel shifters

c. Parity detectors

d. Ripple carry adders

e. Look ahead carry adder

f. Combinational multipliers

5. ASIC Design and synthesis of sequential logic (RTL using VHDL)

a. Latch based design and synthesis

b. Flip-flop based design and synthesis

c. Clock and resets

d. Single clock domain designs

e. Multiple clock domain designs

f. Timing parameters and design operating frequency

g. Counter design using VHDL

h. Shift register design using VHDL

6. ASIC design guidelines

a. Design partitioning

b. Parallel and priority logic

c. Data path and control path synthesis

d. Grouping

e. Using signals and variables

f. Resource sharing

g. Logic duplications

h. Clock network and Clocking policies

i. Reset and reset policies

j. Pipelining

k. Guidelines for the multiple clock domains

l. Power improvement

7. ASIC RTL Verification

a. ASIC Verification flow

b. Verification using VHDL

c. Verification architecture

d. Verification planning

e. Case study

8. FSM using VHDL and synthesis

a. Moore and mealy machine

b. Controller design using FSM

c. FSM performance improvement techniques

d. FSM Synthesis guidelines

e. Design using FSM and issues.

f. Case study

i. Sequence detectors

ii. Parity detection and generations

iii. Ring and Johnson counters and controllers

9. ASIC design improvement techniques

a. Area minimization techniques

b. Speed improvement techniques

c. Low power design techniques

d. Case study

i. RTL design and verification using VHDL

ii. Synthesis

iii. Timing closure

iv. Performance improvement

10. ASIC Synthesis using Synopsys DC

a. ASIC synthesis flow

b. Constraints

i. Area

ii. Speed

iii. Power

c. ASIC synthesis commands and use

d. Synthesis scripts

e. Synthesis reports

f. Case study of FSM controller and synthesis

11. Design for Testability

a. DFT basics

b. DFT flow

c. Faults in design

d. Full scan and partial scan chain

e. Fault simulation

f. Impact on area, speed and power

g. DFT reports

h. BIST

i. Case study

12. Static timing analysis

a. STA Vs DTA

b. STA flow

c. STA commands using Synopsys PT

d. Timing paths

e. Set up and hold slack

f. Frequency calculations

g. Design performance improvements

h. Pre layout Timing closure using Synopsys PT

i. Timing reports

j. Case study

13. Multiple Clock domain designs

a. Single vs. multiple clock domain designs

b. Synchronous FIFO

i. RTL design using VHDL

ii. Synthesis, DFT

iii. Pre layout STA

c. Asynchronous FIFO

i. RTL design using VHDL

ii. Synthesis, DFT

iii. Pre layout STA

d. FIFO design scenarios

e. FIFO depth calculations

14. Low power ASIC design

a. Low power designs and formats

b. Low power design techniques

c. Low power design flow

d. Low power architectures for ASIC

e. Low power design scenarios

15. ASIC Physical design

a. Floor planning

b. Power planning

c. Clock tree synthesis

d. Placement and routing

e. Post layout STA

f. RC extraction

g. Design timing closure and checks

h. Mask preparation

Appendix

1. Tcl-tk commands

2. Synopsys DC commands

3. Synopsys PT commands

4. Programmable ASICs and recent trends