[eBook Code] Transient-Induced Latchup in CMOS Integrated Circuits (eBook Code, 1st)

Preface.

1 Introduction.

1.1 Latchup Overview.

1.2 Background of TLU.

1.3 Categories of TLU-Triggering Modes.

1.4 TLU Standard Practice.

References.

2 Physical Mechanism of TLU under the System-Level ESD Test.

2.1 Background.

2.2 TLU in the System-Level ESD Test.

2.3 Test Structure.

2.4 Measurement Setup.

2.5 Device Simulation.

2.6 TLU Measurement.

2.7 Discussion.

2.8 Conclusion.

References.

3 Component-Level Measurement for TLU under System-Level ESD Considerations.

3.1 Background.

3.2 Component-Level TLU Measurement Setup.

3.3 Influence of the Current-Blocking Diode and Current-Limiting Resistance on the Bipolar Trigger Waveforms.

3.4 Influence of the Current-Blocking Diode and Current-Limiting Resistance on the TLU Level.

3.5 Verifications of Device Simulation.

3.6 Suggested Component-Level TLU Measurement Setup.

3.7 TLU Verification on Real Circuits.

3.8 Evaluation on Board-Level Noise Filters to Suppress TLU.

3.9 Conclusion.

References.

4 TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits.

4.1 Examples of Different DFreq and DFactor in the System-Level ESD Test.

4.2 TLU Dependency on DFreq and DFactor.

4.3 Experimental Verification on TLU.

4.4 Suggested Guidelines for TLU Prevention.

4.5 Conclusion.

References.

5 TLU in CMOS ICs in the Electrical Fast Transient Test.

5.1 Electrical Fast Transient Test.

5.2 Test Structure.

5.3 Experimental Measurements.

5.4 Evaluation on Board-Level Noise Filters to Suppress TLU in the EFT Test.

5.5. Conclusion.

References.

6 Methodology on Extracting Compact Layout Rules for Latchup Prevention.

6.1 Introduction.

6.2 Latchup Test.

6.3 Extraction of Layout Rules for I/O Cells.

6.4 Extraction of Layout Rules for Internal Circuits.

6.5 Extraction of Layout Rules between I/O Cells and Internal Circuits.

6.6 Conclusion.

References.

7 Special Layout Issues for Latchup Prevention.

7.1 Latchup Between Two Different Power Domains.

7.2 Latchup in Internal Circuits Adjacent to Power-Rail ESD Clamp Circuits.

7.3 Unexpected Trigger Point to Initiate Latchup in Internal Circuits.

7.4 Other Unexpected Latchup Paths in CMOS ICs.

7.5 Conclusion.

References.

8 TLU Prevention in Power-Rail ESD Clamp Circuits.

8.1 In LV CMOS ICs.

8.2 In HV CMOS ICs.

8.3 Conclusion.

References.

9 Summary.

9.1 TLU in CMOS ICs.

9.2 Extraction of Compact and Safe Layout Rules for Latchup Prevention.

Appendix A: Practical Application?Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.

A.1 For I/O Cells.

A.2 For Internal Circuits.

A.3 For Between I/O and Internal Circuits.

A.4 For Circuits across Two Different Power Domains.

A.5 Suggested Layout Guidelines.

Index.