Designing with FPGAs and CPLDs (Paperback)

Foreward
Preface
Acknowledgments

Chapter 1 Prehistory: Programmable Logic to ASICs
· Programmable Read Only Memories (PROMs)
· Programmable Logic Arrays (PLAs)
· Programmable Array Logic (PALs)
· The Masked Gate Array ASIC
· CPLDs and FPGAs
· Summary
· Exercises

Chapter 2 Complex Programmable Logic Devices (CPLDs)
· CPLD Architectures
· Function Blocks
· I/O Blocks2.4 Clock Drivers
· Interconnect
· CPLD Technology and Programmable Elements
· Embedded Devices
· Summary: CPLD Selection Criteria
· Exercises

Chapter 3 Field Programmable Gate Arrays (FPGAs)
· FPGA Architectures
· Configurable Logic Blocks
· Configurable I/O Blocks
· Embedded Devices
· Programmable Interconnect
· Clock Circuitry
· SRAM vs. Antifuse Programming
· Emulating and Prototyping ASICs
· Summary
· Exercises

Chapter 4 Universal Design Methodology for Programmable Devices
· What is UDM and UDM-PD?
· Writing a Specification
· Specification Review
· Choosing Device and Tools
· Design
· Verification
· Final Review
· System Integration and Test
· Ship Product!
· Summary
· Exercises

Chapter 5 Design Techniques, Rules, and Guidelines
· Hardware Description Languages
· Top-Down Design
· Synchronous Design
· Floating Nodes
· Bus Contention
· One-Hot State Encoding
· Design For Test (DFT)
· Testing Redundant Logic
· Initializing State Machines
· Observable Nodes
· Scan Techniques
· Summary
· Exercises

Chapter 6 Verification
· What is Verification?

· Simulation
· Static Timing Analysis
· Assertion Languages
· Formal Verification
· Summary
· Exercises

Chapter 7 Electronic Design Automation Tools
· Simulation Software
· Testbench Generators
· In Situ Tools
· Synthesis Software
· Automatic Test Pattern Generation (ATPG)
· Scan Insertion Software
· Built-In Self-Test (BIST) Generators
· Static Timing Analysis Software
· Formal Verification Software
· Place and Route Software
· Programming Tools
· Summary
· Exercises

Chapter 8 Today and The Future
· Cores
· Special I/O Drivers
· New Architectures
· ASICs with Embedded FPGA Cells
· Summary

Appendix A Answer Key

Appendix B Verilog Code for Schematics in Chapter 6

Glossary
References
About the Author
Index