Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, Patmos 2004, Santorini, Gre (Paperback, 2004)

Keynote Speech.- Connecting E-Dreams to Deep-Submicron Realities.- Invited Talks.- Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.- Low-Voltage Embedded RAMs - Current Status and Future Trends.- Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing.- Embedded Tutorials.- Leakage in CMOS Circuits - An Introduction.- The Certainty of Uncertainty: Randomness in Nanometer Design.- Session 1: Buses and Communication.- Crosstalk Cancellation for Realistic PCB Buses.- A Low-Power Encoding Scheme for GigaByte Video Interfaces.- Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.- Perfect 3-Limited-Weight Code for Low Power I/O.- A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses.- Session 2: Circuits and Devices (I).- Performance Metric Based Optimization Protocol.- Temperature Dependence in Low Power CMOS UDSM Process.- Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.- High Yield Standard Cell Libraries: Optimization and Modeling.- A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.- Session 3: Low Power (I).- Sleepy Stack Reduction of Leakage Power.- A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.- Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.- Reducing Cross-Talk Induced Power Consumption and Delay.- Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.- Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.- Session 4: Architectures.- Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS.- Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.- Register Isolation for Synthesizable Register Files.- Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures.- Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.- Session 5: Asynchronous Circuits.- GALSification of IEEE 802.11a Baseband Processor.- TAST Profiler and Low Energy Asynchronous Design Methodology.- Low Latency Synchronization Through Speculation.- Minimizing the Power Consumption of an Asynchronous Multiplier.- A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.- Session 6: System Design.- L0 Cluster Synthesis and Operation Shuffling.- On Combined DVS and Processor Evaluation.- A Multi-level Validation Methodology for Wireless Network Applications.- SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.- Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards.- Towards a Software Power Cost Analysis Framework Using Colored Petri Net.- Session 7: Circuits and Devices (II).- A 260ps Quasi-static ALU in 90nm CMOS.- Embedded EEPROM Speed Optimization Using System Power Supply Resources.- Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.- A Predictive Synchronizer for Periodic Clock Domains.- Power Supply Net for Adiabatic Circuits.- Session 8: Interconnect and Physical Design.- A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.- Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.- An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.- Wirelength Reduction Using 3-D Physical Design.- On Skin Effect in On-Chip Interconnects.- Session 9: Security and Safety.- A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.- A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.- A Flexible and Accurate Energy Mod