Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, Patmos 2005, Leuven, Belgiu (Paperback, 2005)

'Session 1: Low-Power Processors.- A Power-Efficient and Scalable Load-Store Queue Design.- Power Consumption Reduction Using Dynamic Control of Micro Processor Performance.- Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications.- Dynamic Instruction Cascading on GALS Microprocessors.- Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.- Session 2: Code Optimization for Low-Power.- A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net.- Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.- Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.- Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications.- Session 3: High-Level Design.- Systematic Preprocessing of Data Dependent Constructs for Embedded Systems.- Temperature Aware Datapath Scheduling.- Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform.- Improving the Memory Bandwidth Utilization Using Loop Transformations.- Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures.- Session 4: Telecommunications and Signal Processing.- Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming.- A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction.- An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments.- Energy-Aware System-on-Chip for 5 GHz Wireless LANs.- Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction.- Session 5: Low-Power Circuits.- An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits.- Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques.- Power Consumption in Reversible Logic Addressed by a Ramp Voltage.- Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing.- Back Annotation in High Speed Asynchronous Design.- Session 6: System-on-Chip Design.- Optimization of Reliability and Power Consumption in Systems on a Chip.- Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs.- A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.- Power Supply Selective Mapping for Accurate Timing Analysis.- Session 7: Busses and Interconnections.- Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.- PSK Signalling on NoC Buses.- Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.- Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing.- Efficient Simulation of Power/Ground Networks with Package and Vias.- Session 8: Modeling.- Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.- Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates.- Compact Static Power Model of Complex CMOS Gates.- Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.- Statistical Critical Path Analysis Considering Correlations.- Session 9: Design Automation.- A CAD Platform for Sensor Interfaces in Low-Power Applications.- An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints.- Efficient Post-layout Power-Delay Curve Generation.- Power - Performance Optimization for Custom Digital Circuits.- Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.- Session 10: Low-Power Techniques.- Logic-Level Fast Current Simulation for Digital CMOS Circuits.- Design of Variable Input Delay Gates for Low Dynamic Power Circuits.- Two-Phase Cloc