책 이미지
책 정보
· 분류 : 외국도서 > 컴퓨터 > 하드웨어 > 네트워크 하드웨어
· ISBN : 9783540726845
· 쪽수 : 829쪽
목차
Track 1: Embedded Architecture.- Object-Orientation Is Evil to Mobile Game: Experience from Industrial Mobile RPGs.- Device-Aware Cache Replacement Algorithm for Heterogeneous Mobile Storage Devices.- The Lightweight Runtime Engine of the Wireless Internet Platform for Mobile Devices.- Product Line Based Reuse Methodology for Developing Generic ECU.- The Object-Oriented Protocol for Data Exchange and Control in Computational-Diverse Embedded Systems.- Track 2: Embedded Hardware.- A Link-Load Balanced Low Energy Mapping and Routing for NoC.- Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor.- Memory Offset Assignment for DSPs.- A Subsection Storage Policy in Intelligent RAID-Based Object Storage Device.- Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.- Theory and Practice of Probabilistic Timed Game for Embedded Systems.- A Design Method for Heterogeneous Adders.- FPGA Based Implementation of Real-Time Video Watermarking Chip.- A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching.- Track 3: Embedded Software.- Function Inlining in Embedded Systems with Code Size Limitation.- Performance Characteristics of Flash Memory: Model and Implications.- A New Type of Embedded File System Based on SPM.- An Efficient Buffer Management Scheme for Implementing a B-Tree on NAND Flash Memory.- A Code Generation Framework for Actor-Oriented Models with Partial Evaluation.- Power-Aware Software Prefetching.- Fast Initialization and Memory Management Techniques for Log-Based Flash Memory File Systems.- Track 4: HW-SW Co-design and SoC.- An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix.- Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips.- Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator.- Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.- NISD: A Framework for Automatic Narrow Instruction Set Design.- A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems.- Face Detection on Embedded Systems.- Track 5: Multimedia and HCI.- An Improved Fusion Design of Audio-Gesture for Multi-modal HCI Based on Web and WPS.- User-Customized Interactive System Using Both Speech and Face Recognition.- Visualization of GML Map Using 3-Layer POI on Mobile Device.- Speaker Recognition Using Temporal Decomposition of LSF for Mobile Environment.- Voice/Non-Voice Classification Using Reliable Fundamental Frequency Estimator for Voice Activated Powered Wheelchair Control.- MPEG-4 Scene Description Optimization for Interactive Terrestrial DMB Content.- A Distributed Wearable System Based on Multimodal Fusion.- Track 6: Pervasive/Ubiquitos Computing and Sensor Network:.- Randomized Approach for Target Coverage Scheduling in Directional Sensor Network.- Efficient Time Triggered Query Processing in Wireless Sensor Networks.- Dependable Geographical Routing on Wireless Sensor Networks.- Minimization of the Redundant Coverage for Dense Wireless Sensor Networks.- Track 7: Power-Aware Computing.- Improved Way Prediction Policy for Low-Energy Instruction Caches.- Sleep Nodes Scheduling in Cluster-Based Heterogeneous Sensor Networks Using AHP.- Energy-Efficient Medium Access Control for Wireless Sensor Networks.- Automatic Power Model Generation for Sensor Network Simulator.- Track 8: Real-Time Systems.- Situation-Aware Based Self-adaptive Architecture for Mission Critical Systems.- Micromobility Management Enhancement for Fast Handover in HMIPv6-Based Real-Time Applications.- DVSMT: Dynamic Voltage Scaling for Scheduling Mixed Real-Time Tasks.- Real-Time Communications on an Integrated Fieldbus Network Based on a Switched Ethernet in Industrial Environment.- On Scheduling Exception Handlers in Dynamic, Embedded Real-Time Systems.- PR-MAC: Path-Oriented Real-Time MAC Protocol for Wirel