Verilog Hdl Design Examples (Hardcover)

Preface Chapter 1 Introduction to Logic Design Using Verilog HDL 1.1 Language Elements 1.2 Expressions 1.3 Modules and Ports 1.4 Built-In Primitives 1.5 User-Defined Primitives 1.6 Dataflow Modeling 1.7 Behavioral Modeling 1.8 Structural Modeling 1.9 Tasks and Functions 1.10 Problems Chapter 2 Combinational Logic Design Using Verilog HDL 2.1 Number Systems 2.2 Boolean Algebra 2.3 Logic Equations 2.4 Multiplexers 2.5 Comparators 2.6 Programmable Logic Devices 2.7 Additional Design Examples 2.8 Problems Chapter 3 Sequential Logic Design Using Verilog HDL 3.1 Introduction 3.2 Synchronous Sequential Machines 3.3 Asynchronous Sequential Machines 3.4 Pulse-Mode Asynchronous Sequential Machines 3.5 Problems Chapter 4 Computer Arithmetic Design Using Verilog HDL 4.1 Introduction 4.2 Fixed-Point Addition 4.3 Fixed-Point Subtraction 4.4 Fixed-Point Multiplication 4.5 Fixed-Point Division 4.6 Arithmetic and Logic Unit 4.7 Decimal Addition 4.8 Decimal Subtraction 4.9 Decimal Multiplication 4.10 Decimal Division 4.11 Floating-Point Addition 4.12 Floating-Point Subtraction 4.13 Floating-Point Multiplication 4.14 Floating-Point Division 4.15 Problems Appendix A Event Queue Appendix B Verilog Project Procedure Appendix C Answers to Select Problems Index