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· 분류 : 외국도서 > 컴퓨터 > 컴퓨터 엔지니어링
· ISBN : 9781439811245
· 쪽수 : 971쪽
목차
Chapter 1 Number Systems and Number Representations
Number Systems
Number Representations
Chapter 2 Logic Design Fundamentals
Boolean Algebra
Minimization Techniques
Combinational Logic
Sequential Logic
Chapter 3 Introduction to Verilog HDL
Built-In Primitives
User-Defined Primitives
Dataflow Modeling
Behavioral Modeling
Structural Modeling
Chapter 4 Fixed-Point Addition
Ripple-Carry Addition
Carry Lookahead Addition
Carry-Save Addition
Memory-Based Addition
Carry-Select Addition
Serial Addition
Chapter 5 Fixed-Point Subtraction
Twos Complement Subtraction
Ripple-Carry Subtraction
Carry Lookahead Addition/Subtraction
Behavioral Addition/Subtraction
Chapter 6 Fixed-Point Multiplication
Sequential Add-Shift Multiplication
Booth Algorithm Multiplication
Bit-Pair Recoding Multiplication
Array Multiplication
Table Lookup Multiplication
Memory-Based Multiplication
Multiple-Operand Multiplication
Chapter 7 Fixed-Point Division
Sequential Shift-Add/Subtract Restoring Division
Sequential Shift-Add/Subtract Nonrestoring Division
SRT Division
Multiplicative Division
Array Division
Chapter 8 Decimal Addition
Addition With Sum Correction
Addition Using Multiplexers
Addition With Memory-Based Correction
Addition With Biased Augend
Chapter 9 Decimal Subtraction
Subtraction Examples
Two-Decade Addition/Subtraction Unit for A+B and A?B
Two-Decade Addition/Subtraction Unit for A+B, A?B, and B?A
Chapter 10 Decimal Multiplication
Binary-to-BCD Conversion
Multiplication Using Behavioral Modeling
Multiplication Using Structural Modeling
Multiplication Using Memory
Multiplication Using Table Lookup
Chapter 11 Decimal Division
Restoring Division ? Version 1
Restoring Division ? Version 2
Division Using Table Lookup
Chapter 12 Floating-Point Addition
Floating-Point Format
Biased Exponents
Floating-Point Addition
Overflow and Underflow
General Floating-Point Organization
Verilog HDL Implementation
Chapter 13 Floating-Point Subtraction
Numerical Examples
Flowcharts
Verilog HDL Implementations
Chapter 14 Floating-Point Multiplication
Double Bias
Flowcharts
Numerical Examples
Verilog HDL Implementations
Chapter 15 Floating-Point Division
Zero Bias
Exponent Overflow/Underflow
Flowcharts
Numerical Examples
Chapter 16 Additional Floating-Point Topics
Rounding Methods
Guard Bits
Verilog HDL Implementations
Chapter 17 Additional Topics in Computer Arithmetic
Residue Checking
Parity-Checked Shift Register
Parity Prediction
Condition Codes for Addition
Logical and Algebraic Shifters
Arithmetic and Logic Units
Count-Down Counter
Shift Registers
Appendices
Index
