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· 분류 : 외국도서 > 컴퓨터 > 컴퓨터 엔지니어링
· ISBN : 9781498738224
· 쪽수 : 846쪽
· 출판일 : 2015-10-28
목차
Introduction to Verilog HDL
Built-In Primitives
User-Defined Primitives
Dataflow Modeling
Behavioral Modeling
Structural Modeling
Problems
Synthesis of Synchronous Sequential Machines 1 Using Verilog HDL
Synchronous Registers
Synchronous Counters
Moore Machines
Mealy Machines
Moore?Mealy Equivalence
Output Glitches
Problems
Synthesis of Synchronous Sequential Machines 2 Using Verilog HDL
Multiplexers for δ Next-State Logic
Decoders for λ Output Logic
Programmable Logic Devices
Iterative Networks
Error Detection in Synchronous Sequential Machines
Problems
Synthesis of Asynchronous Sequential Machines Using Verilog HDL
Introduction
Synthesis Examples
Problems
Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL
Introduction
Synthesis Examples
Problems
Appendix A: Event Queue
Appendix B: Verilog Project Procedure
Appendix C: Answers to Select Problems
