Layout Optimization in VLSI Design (Hardcover, 2001)

Preface. 1. Integrated Floorplanning and Interconnect Planning; H.-M. Chen, et al. 2. Interconnect Planning; J. Cong. 3. Modern Standard-cell Placement Techniques; X. Yang, et al. 4. Non-Hanan Optimization for Global VLSI Interconnect; J. Hu, S.S. Sapatnekar. 5. Techniques for Timing-Driven Routing; J. Lillis. 6. Interconnect Modeling and Design with Consideration of Inductance; L. He. 7. Modeling and Characterization of IC Interconnects and Packagings for the Signal Integrity Verification on High-Performance VLSI Circuits; Y. Eo. 8. Tradeoffs in Digital Binary Adder Design: the Effects of Floorplanning, Number of Levels of Metals, and Supply Voltage on Performance and Area; V. Kantabutra, et al.