SystemVerilog 언어 문법 실습하며 배우기

1. Literal Values
1.1. Literal Values
1.2. Lab : Integer and Logic Literals
1.3. Lab : Real Literals
1.4. Lab : Time Literals
1.5. Lab : String Literals
1.6. Lab : Array Literals
1.7. Lab : Structure Literals

2. Data types
2.1. Data Types
2.2. Lab : Integer Data Type
2.3. Lab : String Data Type
2.4. Lab : Event Data Type
2.5. Lab : Array Type Definition
2.6. Lab : Enumeration Type Definition
2.7. Lab : Structure Type Definition
2.8. Lab : Union Type Definition
2.9. Lab : Static Casting
2.10. Lab : Dynamic Casting

3. Array
3.1. Arrays
3.2. Lab : Packed and Unpacked Array
3.3. Lab : Dynamic Array
3.4. Lab : Associative Array
3.5. Lab : Queue

4. Classes
4.1. Classes
4.2. Lab : Constant and Static
4.3. Lab : Inheritance
4.4. Lab : Encapsulation
4.5. Lab : Parameter

5. Operations and Expressions
5.1. Operations and Expressions
5.2. Lab : Assignment Operators
5.3. Lab : Logic and Bit Types Operator
5.4. Lab : Wild Equality and Inequality Operator
5.5. Lab : Structure Member Assignment
5.6. Lab : Union Member Assignment
5.7. Lab : Streaming Operators (pack/unpack)
5.8. Lab : Set Membership Operator (inside)

6. Procedural Statements
6.1. Procedural Statements
6.2. Lab : If-Then-Else Statements
6.3. Lab : Case Statements
6.4. Lab : Loop Statements
6.5. Lab : Continue and Break Statements
6.6. Lab : Disable Statement and Statement Label
6.7. Lab : Event Control
6.8. Lab : Assertion Events

7. Processes
7.1. Processes
7.2. Lab : Combinational Logic
7.3. Lab : Latched Logic
7.4. Lab : Sequential Logic
7.5. Lab : fork-join Statement
7.6. Lab : fork-join_any Statement
7.7. Lab : fork-join_none Statement
7.8. Lab : wait fork Statement
7.9. Lab : Disable fork Statement\

8. Tasks and Functions
8.1. Tasks and Functions
8.2. Lab : Task
8.3. Lab : Function Return Value
8.4. Lab : Argument Passing by Ref
8.5. Lab : Argument Default Value

9. Random Constraints
9.1. Random Constraints
9.2. Lab : Random Variables and Constraints
9.3. Lab : Disabling Random Variable and Constraints
9.4. Lab : Random Constraints with Inside
9.5. Lab : Randomize With Statement
9.6. Lab : Pre_randomize and Post_randomize
9.7. Lab : Randomization of Array Size
9.8. Lab : Distribution Control
9.9. Lab : Randomization Ordering
9.10. Lab : Random Weighted Cases

10. Interprocess Synchronization and Communication
10.1. Interprocess Synchronization and Communication
10.2. Lab : Semaphore
10.3. Lab : Mailbox
10.4. Lab : Event

11. Clocking Blocks
11.1. Clocking Blocks
11.2. Lab : Default Clocking Blocks
11.3. Lab : Clocking Skews

12. Program Block
12.1. Program Block
12.2. Lab : Simple Program Block
12.3. Lab : Program Block with Interface

13. Hierarchy
13.1. Hierarchy
13.2. Lab : Package Import
13.3. Lab : Hierarchy
13.4. Lab : Nested Module
13.5. Lab : Parameterized Module

14. Interfaces
14.1. Interfaces
14.2. Lab : Bundle Interface
14.3. Lab : Modport Interface
14.4. Lab : Clocking Block and Modport
14.5. Lab : Tasks in Interface

15. System Tasks and System Functions
15.1. System Tasks and System Functions
15.2. Lab : System Tasks on Variables
15.3. Lab : System Tasks on Arrays
15.4. Lab : System Tasks of General File Read/Write
15.5. Lab : System Tasks of Memory File Read/Write

16. Assertions
16.1. Assertions
16.2. Lab : Immediate Assertions
16.3. Lab : Concurrent Assertion
16.4. Lab : Sequences

17. Coverage
17.1. Coverage
17.2. Lab : Simple Coverage
17.3. Lab : Various Coverage Cases
17.4. Lab : Transition Coverages
17.5. Lab : Wildcard Coverages
17.6. Lab : Cross Coverages

18. Design Examples
18.1. Lab : Combinational Logic (Full Adder)
18.2. Lab : Sequential Logic (Shift Register)
18.3 Lab : Finite State Machine (Sequence Detector)
18.4. Lab : Master and Slave Communication

부록 1. 공학용 SaaS 기반 임베디드 시스템 설계용 CAD 시스템, Flowrian2
부록 1.1. Flowrian2의 독창성
부록 1.2. 웹 기반 CAD 시스템
부록 1.3. Flowrian2 의 설치
부록 1.4. SystemVerilog 설계 및 시뮬레이션 검증 흐름