eMMC 메모리 반도체 개발을 쉽게 이해하기

목차

1. eMMC 개요 20
1-1. eMMC System 개요 20
1-2. System 특징 20
1-3. System 동작 전압 구성 21
1-4. 기본 동작 전압의 Timing 설명 21
1-5. Bus Protocol 22
1-6. Register 종류 23
1-6-1. CID Fields : 16 bytes 23
1-6-2. RCA register : 2 bytes 24
1-6-3. DSR register content : 2 bytes 24
1-6-4. CSD Fields 24
1-6-5. OCR register 25
1-6-6. EXT_CSD fields : 512 bytes 26
1-7. 동작 명령어들 31
1-8. 주요 State diagram 35
1-8-1. eMMC state diagram (boot mode) 35
1-8-2. eMMC state diagram (Card identification mode) 35
1-8-3. eMMC state diagram (data transfer mode) 36
1-8-4. eMMC state transition diagram, interrupt mode 37
1-9. Multiple-block의 CMD, Data 간의 기본 동작 37
1-9-1. Multiple-block read operation 37
1-9-2. Multiple-block write operation 37
1-9-3. No ‘response’ and ‘no data’ operations 38

2. eMMC Hardware 39
2-1. Power supply 39
2-1-1. eMMC eMMC internal power diagram 39
2-1-2. e2MMC internal power diagram 39

2-2. High Speed System Block diagram 40
2-2-1. HS200 System Block diagram 40
2-2-2. HS400 System Block diagram 41

2-3. eMMC Power-up 41
2-3-1. eMMC voltage combinations 41
2-3-2. Power supply Voltages 42
2-3-3. Power-up 42
2-3-4. Power-up diagram 42
2-3-5. eMMC power-up diagram 44
2-3-6. eMMC power-up guidelines 44
2-3-7. eMMC power cycle 45

2-4. eMMC bus 46
2-4-1. Bus circuitry diagram 46
2-4-2. Bus signal levels 47
2-4-3. Programmable Card output driver 48
2-4-4. DSR register content 48
2-4-5. eMMC bus driver 48
2-4-6. Bus signal line load 49
2-4-7. Capacitance and Resistors 50
2-4-8. Bus general operating conditions 50
2-4-9. High-speed eMMC bus functions 51
2-4-9-1. Bus initialization 51
2-4-10. Bus Operating Conditions for HS200 and HS400 52
2-4-11. Card Output Driver Requirements for HS200 and HS400 52
2-4-11-1. Driver Types Definition 52
2-4-11-2. I/O driver strength types 52
2-4-12. Driver Type-0 AC Characteristics 53
2-4-12-1. Driver Type-0 AC Characteristics 53
2-4-12-2. Driver Type-0 Test Circuit 53
2-4-12-3. Outputs test circuit for rise/fall time measurement 53
2-4-13. Driver Type Selection 54

2-5. Bus Speed Modes 54
2-5-1. eMMC에서 제공하는 다양한 Bus Speed 모드 54
2-5-2. High Speed mode 특징 54
2-5-3. 데이터 Bus width 변경 55
2-5-4. XNOR values 55
2-5-5. Switching to high-speed mode 56
2-5-6. Speed class definition 56
2-5-7. Measurement of the performance 57

2-6. Block operation 57
2-6-1. Multiple-block operation 57
2-6-1-1. Multiple-block read operation 57
2-6-1-2. Multiple-block write operation 58
2-6-1-3. No ‘response’ and ‘no data’ operations 58

2-7. Token format 개념 58
2-7-1. Command token format : 명령 토큰 형식 59
2-7-2. Response token format 59
2-7-3. SDR (Single Data Rate)용 Data packet format 59
2-7-3-1. 1 Bit bus (only DAT0 사용) 59
2-7-3-2. 4 Bits bus (DAT0 ~ DATA3 사용) 60
2-7-3-3. 8 Bits bus (DAT0 ~ DAT7 사용) 60
2-7-4. DDR (Double Data Rate)용 Data packet format 60
2-7-4-1. 4 Bit bus DDR (DAT0 ~ DAT3 사용) 61
2-7-4-2. 8 Bit bus DDR (DAT0 ~ DAT7 사용) 61
2-7-4-3. 8 Bit bus DDR for HS400 output (DAT7 ~ DAT0 사용) 62
2-7-5. DDR52용 CRC status token 63
2-7-5-1. Positive CRC status token (‘010’) 또는 Boot 인지 패턴일 경우 63
2-7-5-2. Negative CRC status token (‘101’)일 경우 63
2-7-5-3. HS400용 status CRC token 64
2-7-5-4. Positive CRC status token (‘010’)일 경우 64
2-7-6-5. Negative CRC status token (‘101’)일 경우 64
2-7-6. Error conditions 64
2-7-6-1. CRC and illegal command 64

2-8. Timings 64
2-8-1. Clock control 65
2-8-2. Command and response 65
2-8-2-1. Identification timing (Card identification mode) 65
2-8-2-2. SET_RCA timing (Card identification mode) 66
2-8-2-3. Command response timing (data transfer mode) 66
2-8-2-4. R1b response timing 66
2-8-2-5. R1b Timing 66
2-8-2-6. Timing response end to next command start (data transfer mode) 66
2-8-2-7. Timing of command sequences (all modes) 67
2-8-3. Data read 67
2-8-3-1. Single-block read timing 67
2-8-3-2. Multiple-block read timing 68
2-8-3-3. Stop command timing (CMD12, data transfer mode) 68
2-8-3-4. Read ahead in multiple block read operation 68
2-8-3-5. Data Strobe Read Timing 68
2-8-3-6. HS400 Read Timing with data block size of 512 bytes 68
2-8-3-7. Read Block Gap 69
2-8-3-8. Clock Stop Timing at Block Gap in Read Operation 69
2-8-4. Data write 69
2-8-4-1. Block write command timing 70
2-8-4-2. Multiple-block write timing 70
2-8-4-3. HS400 Write Timing 71
2-8-4-4. HS400 Write Timing with data block size of 512 bytes 71
2-8-4-5. NCRC timing 71
2-8-4-6. BUSY Signal after CRC Status Response 71
2-8-5. Stop transmission 72
2-8-5-1. Stop transmission during data transfer from the host 72
2-8-5-2. Stop transmission during CRC status transfer from the Card 72
2-8-5-3. Stop transmission after last data block; Card is busy programming 73
2-8-5-4. Reselecting a Busy Card 73
2-8-5-5. Stop transmission after last data block; Card becomes busy 73
2-8-5-6. Stop transmission timing 74
2-8-5-7. Stop transmission just before CRC status transfer from the Card 74
2-8-5-8. Stop transmission during CRC status transfer from the Card - 1 74
2-8-5-9. Stop transmission during CRC status transfer from the Card - 2 74
2-8-6. CMD12 Timing Modification 75
2-8-6-1. CMD12 Timing Modification in Write Operation 75
2-8-6-2. Border Timing of CMD12 in Write Operation 75
2-8-6-3. CMD12 Timing Modification in Read Operation 75
2-8-6-4. Border Timing of CMD12 in Read Operation 76
2-8-7. Enhanced Strobe in HS400 Mode 76
2-8-7-1. Enhanced Strobe signals for CMD Response and Data Out (Read operation) 76
2-8-7-2. Enhanced Strobe signals for CMD Response and CRC Response (Write operation) 76
2-8-7-3. HS400 mode change with Enhanced Strobe 77
2-8-8. Bus test procedure timing 77
2-8-8-1. Bus test procedure timing 77
2-8-9. Boot operation 77
2-8-9-1. Boot operation, termination between consecutive data blocks 77
2-8-9-2. Boot operation, termination during transfer 78
2-8-9-3. Bus mode change timing (push-pull to open-drain) 78
2-8-10. Alternative boot operation 78
2-8-10—1. Alternative boot operation, termination between consecutive data blocks 78
2-8-10-2. Alternative boot operation, termination during transfer 79

2-9. High speed Timing Values 79
2-9-1. Timing Parameters 79
2-9-2. Timing changes in HS200 and HS400 mode 80
2-9-2-1. Timing values 80
2-9-2-2. Timing Parameters for HS200 and HS400 mode 80
2-9-2-3. Timing diagram : data input / output in single data rate mode 80
2-9-3. Card interface timings 81
2-9-3-1. High-speed Card interface timing 81
2-9-4. Bus Timing Specification in HS200 mode 81
2-9-4-1. HS200 Clock Timing 81
2-9-4-2. HS200 Clock signal timing 81
2-9-4-3. HS200 Clock signal timing table 82
2-9-4-4. HS200 Card Input Timing 82
2-9-4-5. HS200 Card input timing table 82
2-9-4-6. HS200 Card Output Timing 83
2-9-4-7. HS200 Card output timing table 83
2-9-4-8. ∆TPH consideration 84
2-9-5. Bus Timing Specification in HS400 mode 84
2-9-5-1. HS400 Card Input Timing 84
2-9-5-2. HS400 Card input timing table 85
2-9-5-3. HS400 Card Output Timing 85
2-9-5-4. HS400 Card output timing table 85
2-9-5-5. HS400 Capacitance and Resistors 86
2-9-5-6. HS400 Card Command Output Timing 86
2-9-5-7. HS400 CMD Response timing 86
2-9-5-8. HS400 CMD Response timing table 87
2-9-5-9. HS400 reference load 87

2-10. Host Forward/Backward-compatible Card interface timing 88
2-10-1. Forward-compatible host interface timing 88
2-10-2. Backward-compatible Card interface timing 89
2-10-3. Timing diagram : data input / output in dual data rate mode 89
2-10-4. Bus timing for DAT signals during 2x data rate operation 90
2-10-5. High-speed Dual data rate interface timings 90
2-10-6. High-speed Card interface timing 91
2-10-7. Backward-compatible Card interface timing 92

2-11. AC Overshoot/Undershoot Specification 93
2-11-1. Overshoot/Undershoot definition 93

2-12. Partition management 93
2-12-1. Command restrictions 95
2-12-2. Boot partition 95
2-12-2-1. BOOT_SIZE_MULT [226] - EXT_CSD : Boot partition size 96
2-12-2-2. RPMB_SIZE_MULT [168] - EXT_CSD : RPMB Partition Size 96
2-12-3. Handling write protection for each boot area individually 97
2-12-4. Extended Partitions Attribute 97
2-12-5. Configure partitions 98
2-12-6. Flow chart for General Purpose Partitions & Enhanced User Data Area parameter setting 99
2-12-7. Memory array partitioning 101

2-13. Time-out conditions 102

2-14. Error protection 103
2-14-1. Error correction codes (ECC) 103
2-14-2. Cyclic redundancy codes (CRC) 104
2-14-3. CRC7 104
2-14-4. CRC7 generator/checker 104
2-14-5. CRC16 104
2-14-6. CRC16 generator/checker 105

2-15. Temperature Conditions 105
2-15-1. Temperature Conditions per Power Classes (Tcase controlled) 105
2-15-2. Heat Removal - Nomenclatures 106
2-15-3. Package Case Temp (Tc) per current consumption 106

2-16. eMMC standard compliance 107
2-16-1. eMMC host requirements for Card classes 107
2-16-2. New Features List for Card type 108

3. eMMC functional description 110
3-1. Operation mode, Card state, CMD line mode의 상관 관계 110
3-1-1. Open-drain mode bus signal level 110
3-1-2. Push-pull mode bus signal level 111
3-1-3. Push-pull signal level - high-voltage 111
3-1-4. Push-pull signal level - 1.70 V -1.95 V VCCQ voltage Range 111
3-1-5. Push-pull signal level - 1.1 V-1.3 V VCCQ range 111

3-2. Boot mode 111
3-2-1. Card reset to Pre-idle state 111
3-2-2. WP condition transition due to H/W reset assertion 112
3-2-2-1. RST_n signal at the power up period 112
3-2-2-2. H/W reset timing parameters 113
3-2-2-3. H/W reset waveform 113
3-2-2-4. Noise filtering timing for H/W Reset 113
3-2-3. Boot operation mode 114
3-2-3-1. Boot mode timing cycle 114
3-2-4. Alternative boot operation 115
3-2-4-1. Alternative boot mode timing cycle 116
3-2-5. Clarification of RESET_BOOT_BUS_CONDITIONS behavior when CMD0 is issued in IDLE 116
3-2-6. Access to boot partition 117
3-2-7. Boot bus width and data access configuration 118
3-2-8. Boot Partition Write Protection 118
3-2-9. Setting EXT CSD BOOT_WP [173] 118

3-3. Card identification mode 119
3-3-1. Card reset 119
3-3-2. Card identification mode state diagram 120
3-3-3. Access mode validation (higher than 2GB of densities) 120